SU941976A1 - Synchronization device - Google Patents

Description

The invention relates to computing and data transmission tools and can be used in the construction of processing and transmission of information.

The recent creation of a new element base - microprocessors has led to the intensive introduction of computer networks with distributed (decentralized) control into the information collection and processing techniques. The development of such networks is, in particular, on the way of increasing their homogeneity, providing increased flexibility and. survivability, ability to increase productivity, etc. As a result of increasing homogeneity for such networks, it becomes characteristic to use self-synchronization in separate elements or groups of network elements 1 and 2.

The disadvantage of such devices is low system reliability of synchronization, in which a synchronization failure in one element (group of elements) results in the output of the system as a whole.

In addition, there is a different synchronization in the network elements, between which the exchange should be made.

leads to the need in the exchange process to bind read-write signals to both sources of sync pulses, which introduces a certain phase delay in the exchange. If the exchange is carried out in single words, then the specific weight of this delay in the total exchange time can be significant, which at 10 leads to a decrease in the capacity of the exchange channel.

Closest to the invention is a synchronization device comprising a generator, the output of which is connected to the first input of the time interval generator, the second input of which is connected to the output of the trigger, and the output to the input

20 . matching unit, modulo adder two, a threshold unit and an integrator whose input is connected to the output of the matching unit and to the first input of the modulo two modulator, and

25 output through the threshold block - to the zero input of the trigger, the output of which is connected by the second input of the time interval generator, and the split input - with the output of the adder

30 submodule two, the second input is kogog-lg-.

connected to the output of the time interval imager 3.

However, when the clock pulses are turned on in a new generator, the duration of the first pulse in the sequence is not normalized, since it depends on the time the resolution appears on the time slot generator. The presence of a pulse of incomplete duration can lead to a malfunction in the system in which the device is used for synchronization.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that a synchronization device comprising a generator, an integrator, a threshold unit and a matching unit, the integrator output is connected to the input of the threshold unit, the co-pQ holds the counting trigger, the key, the priority signal key, the priority setting node and the comparison circuit, the threshold block contains two threshold elements and an OR-NOT element, and the matching block contains a key, two triggers, four AND elements and an OR element, and the generator output is connected to the input of the counting trigger whose output is connected to the input at the integrator, the key input of the matching block and the first input of the first element And the matching block, the outputs of the first and second elements of the matching block are connected to the single inputs of the first and second triggers of the matching block, respectively, the output of the second trigger of the matching block , the output of which is connected to the second input of the first element AND of the matching block and the common synchronization bus of the device, the input of the threshold block is connected to the inputs of the first and second thresholds the threshold block elements, the outputs of which are connected to the inputs of the OR-NOT element of the threshold block, the priority setting node output is connected with the key input and the first input of the comparison circuit, the second input of which is connected to the output of the priority signal key and the device priority bus connected to the third input of the first and the first inputs of the third and fourth elements AND the matching unit the second inputs of the third and fourth elements AND the matching unit are connected to the output of the OR-NOT element by the HORSE unit and control yuschim input stratum priority key signal, koto cerned input connected to the output key vyho rows of the third and fourth members are connected to the matching unit WMOs OR element matching block

the output of the OR element of the matching unit is connected to the zero inputs of the first and second triggers of the matching unit, the output of the counting trigger is connected to the first input of the second and

the third input of the third element And the matching unit, the output of the first trigger of the matching unit is connected to the second input of the second element And the matching unit.

The drawing shows a block diagram of the device.

The device for synchronization contains a generator of 1 clock pulses connected via a counting trigger 2

to the input of the integrator 3, the output of which is connected to the input of the threshold unit 4, a key 5 connected between the key b of the priority signal and the priority setting unit 7, a comparison circuit 8 whose inputs are connected to the input of the key 5 and the output of the key 6 of the priority signal, and a matching unit 9. The threshold unit 4 contains the threshold elements 10 and 11 and the element OR-NO 12, the output of which is the output of block 4, the inputs of the element OR-NOT are connected to the outputs of the threshold elements 10 and 11, the inputs of which are connected to the output of the integrator 3, the matching unit 9 contains manageable key 13, RS-flip-flops 14 and 15, elements AND 16-19 and element OR 20, Inputs of elements AND 1b-18 are connected to the output of trigger 2. The output of comparison circuit 8 is connected to inputs of elements And 16, 18 and 19. The outputs of elements AND 16 and 17 are connected to the S-inputs of RS flip-flops 14 and 15. respectively. The outputs of the elements 18 and 19 are connected to the inputs of the element OR 20, the output of which is connected to the R-inputs of the RS flip-flops 14 and 15. The output of the element OR-NOT 12 is connected to the inputs of the elements 18 and 19. The control key 13 is connected between the output of the trigger 2 and the common synchronization bus 21, the output of the key 6 is connected to the priority bus 22. The output of the key 13 is connected to the input of the element AND 16, the output of the trigger 15 is connected to the input of the element AND 17. The integrator 3 and the threshold block 4 serve to detect the condition of the failed generator 1. During normal operation of the generator 1, the output of the integrator 3 sets the level x x , where the amplitude of the sync pulses corresponds to the level of the logical unit. In the event of a generator 1 failure, the level at the output of the integrator 3 is set to the same level at the output of trigger 2 (either X, -, or 0). With the help of threshold elements 10 and 11 both of these states are distinguished. It is at the outputs of the threshold elements 10 and 11 that the signals 2 w О t are formed. As a result, at the output of the element OR NOT 12 there appears a logical level corresponding to the operational generator 1, if tt x t, and the level O, if the signal at the output of the integrator 3 exits this interval. Block 9 is used to connect (disconnect) the own generator 1 to the bus 21. During the switching process, the switching moment is linked to the fronts of either the own generator 1 or generator 1 located in another device and currently occupying the 2L bus The use of this reference allowed us to exclude the occurrence at the moment of switching over of the generator 1 of short-length sync pulses, which can lead to faults in synchronized devices. Cable 5 does not have a control input, and its two poles are specialized — one is the input and the other is the output. Key 5 opens if the input level exceeds the level of the output signal. An example of such a key. Can serve as a diode. The device works as follows. Two Ai B synchronization devices interact. During the interaction, an automatic connection is made to the bus 21 of only one of the operational generators 1. It is assumed that the priority of generator 1 in device A is higher than in device B. The process of interaction of a large number of devices generalized in a simple way. Consider three cases that may occur. In the connection of the generator 1 to the bus 21 there can be three cases. In the first case, both the generators 1 of the devices A and B are intact. After the device A is turned on, the output of its integrator 3 is formed. At the outputs of both the signal X 2 of the threshold elements 10 and 11, the level O is set, and the output of the OR-NOT 12 element is set to level 1 B and, as a result, device 6 high, then the key 5 and the bus 22 are set to the priority of device A. The comparison pattern 8 captures this event by issuing a command to connect the generator 1. This command uses the elements 16 and 17 and trigger 15 to assign generator connections 1 to bus 21 along its leading edge. The signal from the output of the element 17, tied to the leading edge of the generator 1, the trigger 14 is set to open the key 13. As a result, the generator 1 of the device A is connected to the bus 21. in the device B in the described case the key 5 remains closed and the command to connect the generator 1 is not formed. . In the second case, the generator 1 in the device A goes out of order. Depending on the state of the trigger 2, at the moment of failure, a level is formed at the output of the threshold element 10 or 11. As a result, a level is set at the output of the element OR NOT 12. The key 6 is locked and on the bus 22 it turns out to be a priority level different from its own priority. The latter is fixed by the comparison circuit 8, the output of the cottara is set to level O. With this level, element 19 and element OR 20 trigger 14 is reset to state O. Key 13 is closed and generator 1 of device A is disconnected from bus 21. In device B bus 22 priority, device A leads to the fact that if its generator 1 is fixed (key 6 is open), then on bus 22 its priority is set. As a result, at the output of the comparison circuit 8, a level is formed, which, similarly to the previous case, is connected to the generator 1 with reference to the leading edge of the sync pulse. In the third case, the generator of the device A, which had previously failed, restores its working capacity. As a result, key 6 is opened in device A and device 22’s priority is set on bus 22. In key B, key 5 is locked, and the output of comparison circuit 8 is set to level through which elements AND and OR 18 and 20 trigger 14 to state O , locking key 13. However, unlike in the previous case, the moment when generator 1 is turned off is associated with the rear ont of the latter in the clock sequence. This allows the own generator 1 to finish the job without changing the duration of the last sync pulse. In turn, the binding of the moment of turning on the generator, torus 1 in device A begins with MOiJteHTa disconnecting generator 1 in device B, which is ensured by the presence of 21 inhibitory inputs in element 16 associated with the bus. Thus, the use of the proposed device to ensure system operability, if at least one generator 1 in one of the synchronization devices functions normally. The design of the matching unit 9 used in this device eliminates the appearance of pulses of incomplete duration both when the generator is turned on and when the generator 1 is turned off, which makes it possible to increase the reliability of the device. Claim device The synchronization device containing a generator, an integrator, a threshold unit and a matching unit, the integrator output being connected to the input of the threshold unit, characterized in that, in order to increase reliability, the device has a counting trigger, a key, a priority signal key, a job node priority and comparison circuit, the second unit contains two threshold elements and the element OR NOT, and the matching unit contains a key, two triggers, four elements AND and the element OR, and the generator output is connected to the input of the counting terminal IGGER whose output is connected to the integrator input, the key input of the matching block and the first input of the first element AND the matching block, the outputs of the first and second elements AND of the matching block are connected to the single inputs of the first and second triggers of the matching block, the output of the second trigger of the matching block Connection to the control input of the key of the matching unit, the output of which is connected to the second input of the first element AND of the matching unit and the general synchronization bus of the device, the input of the threshold unit To the inputs of the first and second threshold elements of the threshold block, the outputs of which are connected to the inputs of the OR-NOT element of the threshold block, the output of the priority node is connected to the key input and the first input of the comparison circuit, the second input of which is connected to the priority key output device, the output of the comparison circuit is connected to the third input of the first and first inputs of the third and fourth elements of the AND matching block, the second inputs of the third and fourth elements of the AND matching block are connected to the output of the the OR of the threshold block and the control input of the priority signal key whose input is connected to the key output, the outputs of the third and fourth elements AND of the matching block are connected to the inputs of the OR element of the matching block, the output of the OR element of the matching block is connected to the zero inputs of the first and the second trigger of the matching unit, the output of the counting trigger is connected to the first input of the second and third inputs of the third elements And the matching unit, the output of the first trigger of the matching unit is connected to the second input of the second of, elements, and matching unit. Sources of information taken into account in the examination 1. Patent SHE number 4021784, .kl. 340-172.5, published. 1977. 2. USSR author's certificate in application 2700938 / 18-24, cl. G About f 1/04, 1979. 3. The author's certificate of the USSR No. 660043, cl. G 06 F 1/04, 1977 (prototype).

Claims (1)

Claim A synchronization device containing __ a generator, an integrator, a threshold block and a matching block, the integrator output being connected to an input of a threshold block, characterized in that, for the purpose of increasing reliability, the device contains a counting trigger, a key, a priority signal key, a task node priority and comparison scheme, the threshold block contains two threshold elements and the element OR — NOT, and the matching block contains the key, two triggers, four AND elements, and the OR element, with the generator output connected to the input of the counting trigger, the output to which is connected to the integrator input 35, the matching block key key · and the first input of the first element AND matching block, the outputs of the first and second elements And matching block are connected .40 connected to the individual inputs of the first and second triggers of the matching block, the output of the second trigger of the matching block by connecting to the control input of the key of the matching unit, the output of which is connected to the second input of the first element AND of the matching unit and the general synchronization bus of the device, the input of the threshold unit is connected to the inputs of the first second threshold elements of the threshold block, the outputs of which are connected to the inputs of the OR — NOT threshold block element, the output of the priority setting node is connected to the key input and the first input of the comparison circuit, the second input of which is connected to the priority signal key output and the device priority bus, circuit output the comparison is connected to the third input of the first and first inputs of the third and fourth elements of the matching block, the second inputs of the third and fourth elements of the matching block are connected to the output of the element OR — NOT the horn unit and the control input of the key of the priority signal, the input of which is connected to the key output, the outputs of the third and fourth elements AND matching block are connected to the inputs of the OR element of the matching block, the output of the OR element of the matching block is connected to the zero inputs of the first and second triggers of the matching block, output the counting trigger is connected to the first input of the second and third input of the third element AND matching block, the output of the first trigger of the matching block is connected to the second input of the second, element AND piling unit.