SU936034A1 - Redundancy storage - Google Patents

Description

(54) RESERVED RECORDING DEVICE

one

This invention relates to memory devices.

A backup memory device is known that contains working and backup memory blocks, address registers, switches, control units 1.

A disadvantage of this device is the limited scope, since it does not counter the malfunctions that occur during operation (faulty cells in the working blocks of these devices must be detected in advance and their contents must be stored in the memory blocks).

The closest technical solution to the proposed is a redundant memory device containing an address register, two working and one backup memory blocks, three switches, a control unit, an adder, a clock generator, and the elements of 2.

The disadvantage of this device is the limited speed due to the output of information from the device output from only one (first or second) working blocks during one memory access, the presence of additional delays in outputting information from the memory for passing information through a series of logic devices (switches , elements And).

A significant increase in memory speed is impossible without increasing the memory block size (word format).

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that the first adder, one of the inputs and outputs of which are connected to the outputs of the backup memory block and one of the information accumulators, is stored in a backup memory device containing the address register, the outputs of which are connected to the inputs of the working and backup memory blocks. inputs of the first switch, the control input of which is connected to the output of the first control unit, and the outputs are connected to the first inputs of the AND elements, the second inputs of which are connected to the generator output

20 Tai TOBbix pulses, and the outputs are one of the outputs of the device, the additional elements And the second switch, the control unit and the adder are introduced, the first inputs of the additional elements And

connected to the outputs of the second switch, second inputs to the output of the clock generator, and outputs to the other outputs of the device, one of the inputs of the second adder connected to the outputs of the backup memory block, others to the outputs of the first working memory block, the inputs of the rip control unit and other information inputs of the first switch, the outputs of the second working memory block are connected to other inputs of the first adder, inputs of the second control unit and one of the information inputs of the second switch, others inform The operational inputs of which are connected to the outputs of the second adder, and the control input is connected to the output of the second control unit.

The drawing shows a functional diagram of the proposed device.

The device contains the address register 1, the first 2 and second 3 working memory blocks, the backup memory block 4, which contains the modulo sum of two information bits of the same name with the same addresses from the working memory blocks 2 and 3, the first control unit 5, the first adder 6, the second adder 7, the second control unit 8, the first 9 and the second 10 switches, And 11 elements, 12 clock pulse generator, And 13 additional elements.

Blocks 5 and 8 controls can implement, for example, the function of byte checking for oddness and be performed on parallel-running integrated circuits 530IP5.

The device works as follows. The address of the cell to be addressed is written to address register 1. The call is made simultaneously to the first 2, second 3 and backup 4 memory blocks at the same addresses. At the same time, the cell of the backup memory block 4 contains the sum modulo two homogeneous bits of the corresponding cells of the first 2 and second 3 memory blocks. The information read from the first working block 2 of the memory enters the control unit 5 at the inputs of the adder 7 and at the inputs of the switch 9. At the same time, the other inputs of the adder 7 receive the information read at the same address from the block 4. The sum is two information, read from blocks 2 and 4, and equal, in the absence of faults, the information read from block 3 of the memory is fed to the inputs of the switch 10.

In a similar way, information read from memory block 3 enters control unit 8, inputs of the accumulator 6 and inputs of the switch 10. Information read by the same address from memory block 4 is received at the inputs of the adder 6. Sum modulo two information read from blocks 3 and 4, and is equal in the absence of faults.

The information read from memory block 2 is fed to the inputs of the switch 9.

If the control unit 5 does not register any distortions in the information coming from unit 2, then the control unit 5 generates a signal allowing the information to pass to the inputs of the And 11 elements through the switch 9. If the control result is negative, then through the switch 9 to the inputs of the And 11 circuit elements

Receives information from the output of the adder 6.

Similarly, if the control unit 8 does not register any distortions of information coming from memory block 3, then the control unit 8 generates a signal allowing the passage of this information through switch 10 to inputs of elements 13. And if the control result is negative, then through switch 10 to inputs elements And 13 comes with information

adder 7 output. At elements 11 and 13, clock pulses from the clock generator 12 produce reliable information (since the inputs of the switches 9 and 10 receive information along different paths, their output may be distorted for some time).

The proposed storage device provides an increase in the size of the transmitted information (in one

Double-bit information is read to the device compared to the memory block size, and the fault of one of the memory blocks or the failure of all memory blocks (if

addresses of failed cells do not match); reducing the cycle time for accessing the memory by reducing delays in the information distribution circuit (in the proposed device, compared to the prototype, switches that are controlled from the address register are excluded).

Claims (1)

Invention Formula A backup memory device containing an address register whose outputs are connected to the inputs of working and backup memory blocks, the first adder, one of the inputs and outputs of which are connected respectively to the outputs of the backup block memory and one of the information inputs of the first switch, the control input of which is connected to the output of the first control unit, and the outputs are connected to the first inputs of the AND elements, the second inputs of which are connected to the generator output clock pulses, and the outputs are one of the outputs of the device, characterized in that, in order to increase the speed of the device, it contains additional elements And the second switch, control unit and adder, the first inputs of the additional elements And connected to the outputs of the second switch, the second the inputs to the output of the clock pulse generator, and the outputs are other outputs of the device, one of the inputs of the second adder is connected to the outputs of the backup memory block, the others to the outputs of the first working memory block, the inputs of the first control unit and other information inputs of the first switch, the outputs of the second working memory unit are connected with other inputs of the first adder, inputs of the second control unit and one of the information inputs of the second switch, the other information inputs of which are connected to the outputs of the second adder, and the control input connected to the output of the second control unit. Sources of information taken into account in the examination 1. US Patent No. 3659275, cl. 340-172.5, published. 1977. 2 USSR Author's Certificate No. 803014, cl. G 11 C 29/00, 1978 (prototype).