SU935914A1 - Multi-phase dc pulse voltage stabilizer - Google Patents

Description

The invention relates to electrical engineering, to devices for stabilizing a constant voltage and can be used in power supply systems of increased reliability. A multi-link pulsed DC voltage regulator is known in which the power part of the device is divided into a number of identical links and, in order to reduce output voltage ripple, the switching of the keys of each link is carried out with a time shift l. A device containing a power unit and a blocking unit is known. The power part consists of several parallel-connected key converting cells (links, modules), made according to the scheme of a single-pulse impulse stabilizer. The switching of the keys of each subsequent cell in relation to the previous one) is carried out with a time shift g / u. where T is the period of switching keys with good cells. Performing the power unit in a modular fashion from a series of interchangeable cells allows the introduction of functionally redundant cells to increase the reliability of the power part of the stabilizer with a relatively small backup ratio. A high removal rate is required. The power part of the stabilizer is ensured; by replacing the failed fecundating cell with an original 2 J. The drawback of the device is the relatively low levels of dependability and repair) of the overall stabilizer of the IICh. The closest technical solution to isotherium is a device containing a power unit and a block yi aalenva. Svpova Honor contains a pair of parallel-connected key images of each type, each of which contains key transistors and LCD filters. For each of the cells, the IH-YA unit contains a pulse-width modular, preamplifiers, measuring devices, and generators. clock pulses and pulse distributor. The key converter cell is made according to the scheme of a one-touch step-down pulsed DC voltage stabilizer. The control of the key transistors of the compensation: type is provided by a pulse-width modulator (with a preamplifier and a measuring device. The time shift in the switching of the transistors is carried out by spreading) by a pulse splitter, made on the basis of EC triggers as a register-distributor Z. The device’s shortness is relatively low levels of dependability and maintainability of the stabilizer as a whole, which is associated with a centralized control unit. The control unit will not be executed on a modular basis due to the clock distributors used in such devices, whose circuits do not allow their division into separate cells due to rigid connections between the elements. This does not allow the stabilizer to be made of individual modules, each of which would include both elements of the power section and elements of the control unit. This circumstance is the cause of the contradictions between high reliability and; maintainability of the power unit and relatively low levels of reliability and maintainability of the control unit 1, and hence the stabilizer: In general, the purpose of the invention is to improve the reliability and maintainability of the multiphase DC voltage regulator. The goal is achieved by the fact that in a multi-phase DC voltage pulse regulator containing a power unit, including AND parallel-connected key educational cells, each -1 of which contains a block of key transistors and an LCD filter, and a control unit containing ø relativity-pulse modulators, outputs connected to the inputs of the corresponding converter cells, and inputs connected to the outputs of the corresponding preamplifiers, measuring units, inputs connected to the output pins It is stabilize the mash, and outputs to the inputs of corresponding preamplifier generators that ry 4 tovyh preobrazovaelnyh pulses by the number of cells podklyuchegshye k6 aspredelitel clock inputs, the outputs of which are connected to each of the preamplifiers. The clock distributor is made of AND AND distributor cells, each 1 of which contains a logic circuit AND, AND -2 logic circuit BAN, logic OR, trigger, delay line, logic expander, prohibition signal sensor, resolution signal sensor, and sensors connected to the choke of the CCL filter -i of the converter cell directly or through a matching transformer, one of the inputs of the circuit I is connected to the clock pulse generator, and the output is connected to the pulmonary modulator of the 1st transform and through the delay line and the first input of the trigger with a different input of the AND circuit, the second trigger input through the OR circuit is connected to the outputs of the BANNER circuits and with the Sensor output of the resolution 1-1 signal of the distribution cell, the signal input of each of the U1 -2 BANNER circuits is connected with the output of the sensor signal of the –fJl distribution cell, and its input is prohibited with the outputs of the interdiction signal from the il-th to -j -j-1st distribution cells directly or through a logic expander. Moreover, the signal transmitter of an eschetet contains a trigger of the initial installation, the output of which is the sensor output, a logic circuit NOT connected in series with the input full wave i receiver and the signal normalization circuit, one of the outputs of which is connected to the first of the trigger inputs of the initial installation, and the other with the second sensor trigger input through the circuits | NOT. In addition, the resolution signal sensor contains serially connected single-half-wave converter, an output connected to the input of the signal normalization circuit, and a short pulse shaper, the output of which is the output of the sensor, and the input of the connectors to the output of the signal normalization circuit of FIG. Figure 1 shows a circuit diagram of a stabilizer for four key converter cells; in fig. 2 - the electrical principle of the distributor {act pulses. The stabilizer contains a power unit and a power unit. The power part is made of four parallel-connected converter cells. The cell consists of a block of key transistors 1 (2 - 4 - for blocks of key transistors of the second, third, fourth cells, respectively), an LCD filter with a linear choke 5 (b - 8 - for the second and subsequent cells, respectively) of a block of reverse diodes 9 ( lO - 12 for the second and subsequent cells, respectively), a block of capacitors 13 (14 16). The control unit contains pulse-width modulators 17 (18-20 for the second and subsequent cells, respectively), preamplifiers 21 (22-24 for the second and subsequent cells), measuring devices 25 (26-28 for the second and subsequent cells), clock generators 29 (30 - 32 - for the second and subsequent cells, respectively), clock distributor 33. Distributor 33 is made of four distribution cells - 34 for the first converter cell, 35 - 37 for the Second and subsequent converter cells permanently. Each distribution cell (Fig. 2) contains a logic circuit AND 37 for the first one, 38-4O for subsequent cells, ilBe a BAN 41 (42 44) and 45 logic circuit (46-48), OR logic 49 (50 - 52), trigger 53 (54 56), delay line 57 (58 - 60), logic expander 61 (62 64), a ban signal sensor 65 (66-, 68), a resolution signal sensor 69 (70 72 ), matching transformer 73 (74 - 76) with three windings - primary 77 and two secondary windings - 78 and 79 (the cw designations of the windings of transformers 74 - 76 in Fig. 3 do not indicate the prohibition signal sensor 65 (B6 - 68)) 3 only revealed yes 65) contains, for example, a full-wave rectifier input 80, a signal sweep circuit 81, a NOT 82 logic circuit and an initial setup trigger 83. The resolution signal sensor 69 (70 72) (only sensor 69 is shown in Fig. 2) contains half-wave input mikhel 84, signal signaling circuit 85, shaper of short pulses 86. Clamp 87-9O entrances of the discharge cells, clamp 91 - their outputs, and clips 95 98 - the inputs of distribution cells.

Terminals of clock pulses 29-32 are connected to terminals 87 - 90

Claims (3)

respectively. To terminals 91 - 94 pulse-pulsed moduli zza 17 20. Clamp 87 (88 - 90) is connected to one of the inputs of the circuit And 37 (38 - 40), and clamp 91 (92 - 94) - with the output of the corresponding circuit And through the delay line 57 (58 -, 60) and the first input of the trigger 53 (54-56) with a different input circuit And 37 (38 - 4O). Clips 95-98 matching transformers are connected to the windings of chokes 5-8, respectively. The prohibition signal sensor 65 (66 - 68) and the signal resolution sensor 69 (7O 72) are connected to the secondary windings of the transfermat 73 (74-76). The output of the prohibition signal sensor 65 of the first cell is connected to the prohibition input of the BAN circuit 42 via a logical extender 62 to the prohibition input of the BAN circuit 46 of the second cell and through the expander 63 to the input of the prohibition of the third cell BAN circuit 47, the output of the 66 cell sensor is connected to the | BAR inputs of the BAN 43 scheme through the extender 63 - the schemes of the PROHIBITION 47 of the third cell; Accordingly, the sensor 67 of the third cell is connected to the inputs of the PROTECTION of the PROHIBITION 44, circuit. h, through the deblorer 64 - schemes; The BANCH 48 of the fourth cell and through the expander 61 are the BANNING schemes of the first cell, and the sensor 68 of the fourth cell is connected to the inputs of the prohibition of the BAN 41 scheme, through the expander 61 - the schema WE-PRET 45 of the first cell and through the expander 62 - the BAN circuit 46 of the second cell . The output of the first cell signal sensor 69 of the first cell is connected to the second circuit OR 50 of the second cell and to the signal inputs of the BANER 43 third cell and 48th fourth circuits. The output of sensor 7 O of the second cell is connected to the circuit OR 51 of the third cell and to the signal inputs of the BAN circuit 44 of the fourth cell and 45 of the first one. Accordingly, the output of the sensor 71 of the third cell is connected to the OR circuit of the fourth cell and to the signal inputs of the BAN circuit 41 of the first and 46 second cells, and the sensor 72 of the fourth cell to the circuit OR 49 of the first cell and the secondary inputs of the BAN circuit 42 of the second 47 of the third cell. The outputs of the BANE cell circuits through the OR 49 (5O - 52) circuit and the second trigger input 53 (54 - 5b) are connected to another input, and 37 (38 - 4b) - 29 32 generators operate siyonfonno, and the failure of any of them does not affect on the synchronous operation of other reHeparqpoB. The operation of the device is considered in the mode of starting and operating the stabilizer, with working cells and in the mode of operation of the stabilizer when one or several converter cells fail. In the mode of starting, the device operates as follows. In the initial state, the key transistors of blocks 1–4 are closed, the current through the linear inductors 5–8 does not flow, there is no voltage on their windings. The voltage at the outputs of the prohibition signal sensors 65–68 and the sensors of the resolution signal 69-72 is equal to the voltage of the logical zero. One of the triggers 53 - 56, for example, the first cell trigger 53, through the installation input is transferred to the state when the voltage of a logical unit is set at its output, the voltage of the logical zero is set at the outputs of the flip-flops 54-56. The trigger 83 of sensor 65 and the corresponding triggers of sensors 66-68 through the installation inputs are switched to the state where the voltage of a logical unit is set at their outputs, whereby the voltage of the logical unit appears at the inputs of the whole circuit. At the outputs of the BREED and connected to them, through the circuits of the IL-I 49 - 52 inputs of the flip-flops 53 - 56, the voltage of the logical zero is set. When voltage is applied to clock generators, the latter begin to generate synchronized pulses. The pulses simultaneously arrive at the input of the circuits I 37-40. At the output of the circuit I 37 of the first cell, a voltage pulse of a single level arrives at the pulse cell. The modulator 17 of the first cell to open the transistors of unit 1. After the pulse passes through the signal communication through the delay line 57, the trigger 53 is brought to the zero state. The transistors of block 1 are opened, and the source of the source flows through the circuit plus the source — the emitter-collector of the transistors of block 1 — the line choke 5 of the filter — load — minus the source. A positive polarity appears on the winding of the throttles 5. The winding of the winding 78 of the transformer 77 is rectified by the two half-wave counter 80 and through the normalization circuit 81 enters the legal input of the trigger 83, confirming the single state of the sensor 41, which exists during the whole period of the cell's work. A positive polarity pulse from the winding 79 through a half-wave rectifier 84 and the normalization circuit 85 is fed to the input of a short pulse shaper 86. The short pulse of the shaper 86 is fed to the input of the OR 50 circuit of the second cell and the signal inputs of the BANNER 43 circuit of the third cell and 48 of the fourth. Since the ban inputs 43 and 48 have a voltage of logical units, the output state of the prohibition schemes does not change. A voltage pulse arriving at the input of the OR 5O circuit causes the appearance of a pulse at its output, which translates the trigger 54 of the second cell into a single state. After a time f And the next, second pulses of the generators 29 - 32 arrive at the inputs of the circuits And 37-40. Since the voltage of the logical unit is only at the second input of the circuit 38 of the second cell, the pulse of the generators goes only to the pulse-width modulator 18 second cell. The transistors of block 2 of the second cell open. A voltage appears on the winding of the line throttle 6. The single signal of the inhibit signal sensor 66 does not change. A short pulse generated by the 7 O, sensor is supplied to the third circuit OR 51 circuit and to the signal inputs of the BANKS 44 fourth and 95 first cells, but as there is a signal at the inputs of the prohibition of the BAN schemes, then the voltage level is zero on the outputs of the BANNERS does not change. The signal received from the output of the 7 O sensor to the input of the OR circuit 63 translates the trigger 55 of the third cell into a single state. After a period of time T / I after the start of the second pulse, the third pulse is fed to the inputs of the circuits And. Since the voltage of a logical unit exists only at the second input of the circuit 39 of the third cell, the clock pulse arrives only at the latitude-pulse modulator 19 of the third cell. An overlap appears on the winding of the line throttle 7. The sensor 71 translates the fourth cell trigger 56 into a single state. The fourth impulse arrives only at the terminal impulse modulator 2 O of the fourth cell, and the fifth impulse - at the modulator 17 of the first cell. Then, the whole cycle when the cell is working properly, the cell repeats, Cell failure, for example, short shutdown (Causes the operation of protection means (for example, fusible protection devices) and the damaged cell is turned off. In the case of a failure, the converter cell also turns off. if one or several ipereating cells fail, the device operates as follows: suppose that the second cell has failed, then the line throttle winding 6 has no voltage, which causes the signal from the circuit input NOT to disappear of the sensor 66 and its triggering to the zero state by the output single signal of the NOT circuit. The signal at the sensor output of the zagdetya 66 takes the zero value. The signal received at the input is locked by the PROTECTION 43 and the signals from the inputs of the expander circuit 63 and 64 are removed The output pulse of the first cell resolution sensor 69, which is fired after switching on the transistors of unit 1, arrives at the signal input of the third cell's BAN 43 circuit and causes a pulse at the output of the OR 51, which translates the trigger 55 into a single unit .. hundred of next clock pulse input to the pulse width modulator 19 pa t and a third cell in place of the failed second cell transistors thus otkroyuts transistor unit 3. Consequently, the second cell is derived from Ref. Further, the entire work cycle is repeated. If another cell fails, for example, the third cell, the signal for the third cell sensor 67 is removed from the input of the fourth cell BANCH 44 and from the input of the expander circuits 64 and 61. Then the sensor signal 69 generated when the first cell transistors are opened is fed to the input the prohibition of the 48th fourth cell, and since the signals of the sensors 66 and 67 are removed from the prohibition input of this circuit, the output of c & we will BAN 48, and therefore the output of the OR 52 circuit, a pulse appears that translates the trigger 56 into a single unit. The next clock pulse, therefore, is fed to the input of a pulse width modulator 2O of the fourth cell. Then the cycle of operation is repeated. This circuit may be paciqxx-Trans on the cells of a multiphase constant-1 stabilizer. This changes the number of schemes; BAN. each distribution cell, equal in the general case, -2, and the number of logic extenders. The proposed circuit ensures the operability of the device 1 failure of all but two cells, while the failure of the output voltage is eliminated. The frequency of operation of cell keys in the event of a failure of 1 cell increases and becomes equal to Dm | where is the frequency of operation of the 1 phi keys and of the original cells. The effect of using a folding device is evaluated by increasing reliability and repairing 1) availability. Indeed, the decentralization of the control unit, which is achieved by the implementation of the distributor from the individual cells, allows the entire stabilizer to be implemented on a modular principle, 1C} and the module includes both the cell and the control unit. In this case, increasing the reliability of the device is achieved by the introduction of {functionally redundant modules. Preliminary calculations show that the stabilizer can be increased to any desired level. Improvement of repairability in case of failure of elements of the power section or control unit is explained by the possibility of repairing the stabilizer by replacing the defective module of the operating stabilizer. Preliminary calculations show that the stabilizer recovery time can be reduced by 10-15 times. Claim 1. Multiphase impulse stabilization Tqp constant voltage, containing a power unit, including And connected key-junction cells, each of which i contains a block of key transistors and an LCD filter and a U1C} block of signals, containing relative-pulse drivers, outputs connected to the inputs of the corresponding cells, and inputs connected to the outputs of the respective teachers, measuring units, inputs connected to the output pins to stabilize CV “in the outputs and - to the inputs of the corresponding preamps, clock pulse generators by the number of converter cells, connected to the clock pulse distributor inputs, the outputs of which are connected to each of the preamplifiers, characterized in that, in order to improve the reliability and maintainability of the stagbilizer, the clock pulse distributor is made and distribution cells, each i of which contains a logic circuit AND, AND -2 logic circuits BANGE, logic circuit OR trigger, delay line, logic circuit extension a sensor, a signal capture sensor, a resolution signal sensor, while the sensors are connected to the choke, the L, CD filter -J of the educational cell directly or through a matching transformer, one of the inputs of the AND circuit is connected to the clock generator, and the output is connected to the latitude a pulse modulator of the first T-type cell of the cell through the delay line and the first trigger input - with another input of the AND circuit, the secondary trigger input through the OR circuit is connected to the outputs of the PROTECTION circuit and with the output of the sensor of the i -1 signal of the distribution signal cells, the signal input of each j th jaa V1-2 of the BANCH circuit is connected to the output of the resolution signal sensor -f - j -1 of the distribution cell, and its input 3ajqjeTa with the outputs of the signal sensors of the zafet from -1 -t to 1 - j -1 cells directly or a logical expander circuit. 2. Stabilizer pop, 1, are distinguished by and with the fact that the signal sensor I ping contains an initial setup trigger, the output of which is a sensor output, a logic circuit NOT, a serially connected input full-wave drive and a signal normalization circuit, one of the outputs of which is connected to the first of the trigger inputs of the initial installation and the other to the second input of the trigger sensor through the circuit is NOT. 3. Stabilizer according to claim 1, characterized in that the resolution signal sensor comprises series half-wave rectifier connected in series, an output connected to the input of a normal signaling circuit, and a short pulse shaper, the output of which is the output of the sensor, and the input connected to the output of the normalization circuit signal. Sources of information taken into account in the examination 1. USSR author's certificate No. .327462, cl. G 05 F 1/56, 1972. 2. Yurchenko, A.I., et al. Multiphase DC Pulse Stabilizer. Electronic technology in automation. Ed. Yu. I. Konev. M., Soviet Radio, 1978, no. 10, fig. 1. with. 108, fig. 2 sec. 111. 3. Yurchenko, A.I., Multiphase pulse stabilizer of constant voltage on high-voltage transistors. Electronic ftexHHK in automation. Under. ed. KZ, I. Konev. M., Soviet radio, 1977, out. 9, fig. 1, s. 57, fig. 2 sec. 59. At 7 - jy 71 je 7s rf & "five p 4G 57 4f J . 9 71 t " five S5 7J1 sp 7S