SU924700A1 - Device for calculating trigonometric functions - Google Patents

Description

() DEVICE FOR CALCULATION OF TRIGONOMETRIC FUNCTIONS

The invention relates to computing and is intended to reproduce functional dependencies in control systems and specialized computers.

A digital device is known with which it is possible to produce discrete values of a sinusoid consisting of a accumulator of a summer adder, a block of gates, a multiplication unit, control keys, and a trigger for the sign of the SE.

The disadvantage of this device is low accuracy due to the fact that at the output of the device, in addition to a sinusoid of the fundamental frequency, there are also sinusoids of frequencies that are multiples of the frequency (K 3 5. 7 .-) of the fundamental frequency, contributing to an error of discrete sinusoids up to 3 6 technical essence to the proposed is

a device 12 comprising a binary counter, three adders, a frequency divider, three And elements and two delay elements, the input of the device connected to the first input of the first adder, the first input of the first And element and through the first delay element to the first input of the second adder, the first input of the second element And the input of the second

10 delay element, the output of which is connected to the first input of the third element And through a counter to the second input of the second element And, the output of which is connected to the second input

15 of the second adder and the second input of the first adder, the output of the second adder is connected to the second input of the first element I, the output of which is connected to the first input of the third

an adder, the output is connected to the second input of the third element MeHta I, the output of which is connected to the third input of the first adder. 39 to the fourth input of which the first output of the frequency divider is connected, the input of which is connected to the output of the second delay element, the second output of the frequency divider is connected to the second input of the third adder. To calculate the values in the device, the method of decomposing trigonometric functions in a power series is implemented, and the first three terms of the series are taken. For example, in calculating a cosine, its decomposition is used in a power series of the following form:. 4 () The disadvantages of the well-known yctpoflstvo is the low accuracy of calculating the values of trigonometric functions and the small area of permissible variation of the argument, equal to a quarter of the period. The low accuracy is due to the fact that the three decomposition terms of the reproduced function in the Taylor series are used for the calculation, with the result that the nullity rapidly increases with increasing argument. Growth error L «4 jf (x) 1 - 4 -2 -COSX. 2 i can be traced to the table data. As can be seen from this table, even at X four times a quarter of the function period, the error of calculating the value of the data function is 2%. The Mala region of possible variation of the argument is a result of an unacceptable increase in error outside the quarter period of the reproduced function, for example. -t, the magnitude of this error is 10.8%. The purpose of the invention is to improve the accuracy of calculating and expanding the range of permissible variation of the argument. The goal is achieved by having a device for calculating trigonometric functions containing a counter, three adders, three And elements, two delay elements and the first frequency divider, and the output of the first element delay, connected to the input of the second delay element, the output of the first frequency divider is connected to the first input of the first adder, the input of the first delay element is connected to the first input of the first element I, O The first delay element is connected to the first input of the second element I, the output of the counter is connected to the second input of the second element I, the output of which is connected to the first input of the second adder, the output of which is connected to the second input of the first element I, the output of which is connected to the first input of the third adder whose output is connected to the first input of the third element I, the output of which is connected to the second input of the first adder, the third and fourth delay elements, the fourth adder, the second, third and fourth d are added frequency modules and the fourth And element, and the device input is connected to the inputs of the second frequency divider and the third delay element, the output of which is connected to the inputs of the first frequency divider and the fourth delay element, the output of which is connected to the second input of the third adder and input the first delay element, the output of which through the third frequency divider is connected to the second input of the second adder, the output of the second delay element through the fourth frequency divider is connected to the input of the counter, the first input to the fourth element The input And is connected to the output of the first adder, the second inputs of the Third and Fourth elements And are connected respectively to the output of the third delay element and the input of the device, the output of the second divider is connected to the first input of the fourth adder, the second input of which is connected to the output of the fourth element I. - the scheme of the proposed device. The device contains an input 1, a divider 2 frequency adder. 3, And k element, delay element 5, adder 6, frequency divider 7, element And 8, delay element 9, adder 10, element 11, delay element 12, adder 13, frequency divider 14, element 15, element 16 ) Aki, frequency divider 17 and counter 18. The initial state of the adder is 3 units in all bits, and adders 6, 10, 13 and counter 18 are zero. The frequency divider 2 divides the number of input pulses by a factor of 8I 00 / tl21. The frequency divider 7 divides the number of input pulses by the factor. Frequency dividers 1 and 17 divide the number of input pulses by 5/2 and 35/2, respectively. The device works as follows. From input 1, a sequence of pulses comes through elements S, 12, 9, and 16 of the delay to the input of a frequency divider 17, from which is reduced 35/2 times this sequence goes to counter 18, made n-bit, binary, in which the code accumulates - About SV С () - 2- - Х2- 55SJ 1-0 This code through the second element 15 is fed to the input of the second adder 13f to the input of the subtraction of which from the output of the frequency divider 1 comes after the weight of the pulses, reduced by 5/2 times. In the second mattress of 13 having 2 bits, the code -1 is turned on. (4 i: -ii - - & S) 2 and the S code through the first element And It is fed to the input of the third adder to, having Sn bits, to the input of the subtraction of which the input is received. handles. The third adder 10 accumulates the code S (x) "(1-6i-i-80x -20xK2. (This code through the third element I is fed to the input of the first adder 6, to the input of the subtraction of which from the output of the frequency divider 7 is followed But the input impulses with a decrease in (O / ZZ times. in the first adder 6, having kn bits, the code r. 1 M S is accumulated (-Ji5 iS 105 10B Code Sj through the fourth element And k is fed to the input of the fourth adder 3, to the input of which subtraction from the output of divider 2 frequency receives a sequence of input pulses, less than 8 00/1121 times. In a quarter ohm adder 3 having 5p bits; the code / Ji ii ILti-Sh. 105 105 41 Po (/.jiivJ-J) ..Jiii)., 515 ".bо 8400, -fn x2 -. (7) accumulates Taking into account the initial state of the fourth adder 3 - units in all bits, the code accumulating in this adder has the following form: -5А уТJ1 Ср 400 iWO In order for adder 3 to accumulate code S (x) (1-6 "tx + 80x - 20x 2-, (9) which corresponds to the polynomial approximating cos2 $ x on the interval O xiV / 2, the number of pulses increased by a factor of 3 times to the input 1 of the device. The positive effect of the invention is to improve the accuracy of calculations of the trigonometric function and expand the range of allowed changes in the argument. The first component of the positive effect - an increase in accuracy is achieved by the fact that the combination of the existing features of the invention corresponds to the approximation of the function V "cos2i X on a polynomial of the form (9), which exactly matches the eye at points x" O, x "1 / IC 1/2 . Consequently, inside the gaps O x 1 / and 1 / x 1/2 there are points corresponding to the maximum approximation error. The magnitude of this error and the coordinates of the points are obtained from the condition that the derivative of the difference d (x) - (1 + 6Ax5 BOX - 20x) is equal to zero (5), (10) i.e. from equation-320x + "Ox-f 2L5 (p25x 0 .. (10 Solving this equation gives x 0, R751, and 0, to which so7; corresponds to dCx), R02147. Comparing the obtained value with the maximum, maximum error of the prototype ((1/2) 0.019969, we find that the accuracy of the present invention is increased more than 9 times. The same set of essential features of the invention reaches 1 0.8660254 0.707107 0.50000 O

coSx

) About 0.0000284 0.000322 0.001796 0.019969 0.108475

invention formula

A device for calculating trigonometric functions comprising a counter, three adders, three amplifiers And, two delay elements and a first frequency divider, the output of the first delay element connected to the input of the second delay element, the output of the first frequency divider connected to the first input of the first adder, the input of the first element the delay is connected to the first input of the first element And, the output of the first delay element is connected to the first input of the second element And, the output of the counter is connected to the second input of the second element And, the output of which It is connected to the first input BTOftoro of the adder, the output of which is connected to the second input of the first element I, the output of which is connected to the first input of the third sum | of the torus, the output of which is connected to the first input of the third element I, the output of which is connected to the second input of the first adder that, in order to improve accuracy, the third and fourth delay elements, the fourth adder, the second, third and fourth frequency dividers and the fourth And element are introduced into it, and the input is 0, 50,000

is connected to the inputs of the second frequency division and the third delay element, the output of which is connected to the inputs of the first frequency divider and the fourth delay element, the output of which is connected to the second input of the third adder and the input of the first delay element, the output of which is via the third frequency divider the adder, the output of the second delay element through the fourth frequency divider is connected to the input of the counter, the first input of the fourth element And is connected to the output of the first adder, the second inputs are the third the first and fourth AND gates respectively connected to the output of the third delay element and the input device, the second splitter output is connected to a first input of the fourth adder, the second input of which is connected to the output of the fourth element I.

Sources of information taken into account in the examination

1. Korshunov Yu.N., Stepashkin A.I. Discrete generator of sinusoidal signals. - Lime universities. Instrumentation, 19b7, t. X. № 11, p. .

2. USSR author's certificate

 560230, cl. G About F 15/3, 1977 (prototype). The second component of the positive effect is the extension of the range of permissible values of the change of the argument by 2 times. At the same time, it is important to note that at the end of the interval at the point X 1/2, the simulating function exactly coincides with the value of the function С0НХ,

Claims (1)

Claim A device for calculating trigonometric functions, comprising a counter, three adders, three integers AND, two delay elements and a first frequency divider, the output of the first delay element being connected to the input of the second delay element, the output of the first frequency divider connected to the first input of the first adder, the input of the first element the delay is connected to the first input of the first element And, the output of the first delay element is connected to the first input of the second element And, the output of the counter is connected to the second input of the second element And, the output of which connected to the first input of the second adder, the output of which is connected to the second input of the first element And, the output of which is connected to the first input of the third adder | whose output is connected to the first input of the third element And, the output of which is connected to the second input of the first adder, characterized in that, in order to increase accuracy, the third and fourth delay elements are introduced into it, • the fourth adder, the second, third and fourth frequency dividers and the fourth AND element, and the input of the device is often connected to the inputs of the second divider s and the third delay element, which is connected to 3D output to the inputs of the first frequency divider and a fourth delay element whose output is connected to a second input of the third adder and the input of the first delay element, the output koto ₃₅ cerned via a third frequency divider connected to the second input of the second adder, the output a second delay element via a fourth frequency divider connected to the counter input ₄₀ a first input of a fourth aND gate connected to the output of the first adder, the second inputs of the third and fourth aND gates are connected soot etstvenno with the output of the third delay element ₄₅ and the input device, the output of the second divider is coupled to a first input of the fourth adder, the second input of which is connected to the output of the fourth element I.