SU921132A1 - Three-channel redundancy pulse device - Google Patents

Description

(5) THREE-CHANNEL RESERVED PULSE DEVICE

Claims (3)

- The invention relates to automation and computing and can be used in digital systems with increased requirements for their reliability. A major-backup pulse device is known which contains in each channel a backup device with feedback circuits, input and output elements OR, and a storage element, with the output of each storage element through the input elements OR connected to the read inputs of two other storage elements 1. When mismatched operation of all three redundant devices, for example, counters, the device adjusts to the time-average signal. The drawback of the device is the obligatory presence of two outputs in each redundant counter, which reduces the reliability of the device as a whole. In addition, the restoration of working capacity by phasing all three sources at the second (in time) signal is unjustified in connection with the available data on the asymmetry of failures of binary recalculation circuits. . A majority-redundant pulsed device is known that has at its output each three storage elements a coincidence, the second inputs of which are connected to the outputs of the input element OR, and the output of each of them with the input of one output element OR 2. This device also requires two outputs in reducible scaling schemes, and the principle of its operation does not take into account the presence of asymmetry of failures of reservable channels, which reduces the reliability of all devices. The closest to the technical essence of this invention is a three-channel major-redundant device containing in each channel backup counters connected to the main memory blocks, prohibition elements, majority elements and an additional memory block, the write and read inputs of which are connected respectively to the output do of the majority element and the output of the backup counter, and the output - to the information inputs of the first and second prohibition elements, the outputs of which are connected respectively to the installation bus both the counter and the read input of the main memory unit, and the inhibiting inputs of the first and second inhibit elements are connected respectively to the input and output of the backup counter. The disadvantage of the device is that all counters accept states similar to the second time counter, i.e. . and this device, in which the property of counters is not taken into account to go after a failure to a higher state with respect to the true state, is not reliable enough. The purpose of the invention. is to increase the reliability of the device. The goal is achieved by the fact that a three-channel redundant impulse device containing a counter, a major element, a memory element and a prohibition element in each channel, a coincidence element, a key and an OR element whose first input is connected to the output of the coincidence element, the second input with the output of the key, and the output with the inputs of the counter installation, the counting input of which is connected to the information input of the key, and the output to the information input of the prohibition element and the corresponding inputs of the majority elements All channels, the output of the major element of each channel is connected to the control input of the key, to the reset input of the memory element and the prohibitive input of the prohibition element whose output is connected to the installation input of the memory element, the output that is connected to the corresponding inputs. match all channels -. FIG. 1 is a functional block diagram of a three-channel reserved pulse device; FIG. 2 are timing diagrams explaining the operation of this device. i The three-channel redundant pulse device (Fig. 1) contains in each channel 1-3 a counter C, a major element 5, a memory block 6, a bar element-7, as well as a coincidence element 8, a key 9 and an element OR 10, the first input of which connected to the output of the coincidence element 8, the second input to the output of the key 9, and the output to the bus of the installation of the counter 4, the input of which is connected to the information input of the key 9 and the output to the informational input of the prohibition element 7 and the corresponding input of the majority element 5- The output of the majority Element 5 is connected to the control Key input 9 to the reset input of memory 6 and prohibiting input of prohibition 7, the output of which is connected to the installation input of memory 6. The output of memory 6 is connected to the corresponding input of the matching element 8, while the corresponding inputs of the elements 8 matches all channels and interconnect the corresponding inputs of the majority elements 5 of all channels. The device works as follows. With synchronous operation of the counters of all three channels 1-3 (Fig. 2A), the signals at their outputs appear simultaneously (Fig. 2A-6, 6, d) and after a time equal to the response time of the majority element, the same signal is also generated on its output (Fig. 2A-d). This signal opens the key 9 prohibits the passage of the signal through the prohibition element 7 and sets the memory unit 6 to zero. It should be noted that if the response time of the majority element 5 is longer than the response time of the prohibition element 7, then the output of the prohibition element 7 may form a narrow a pulse (Fig. 2A-J), which translates memory unit 6 for a short time into a single state (Fig. 2A-U.). The presence of narrow pulses at the outputs of the memory block 6 and at the output of the coincidence element 8 (Fig. 2A-K) does not affect the operation of the device, since simultaneously the installation signal is generated at the output of the key 9 (Fig. 2A-e) OR 10 (2A-F). If a high state of one of the three counters k fails (suppose, for example, this is channel 1 counter), its output signal passes through the open interdiction element 7 and translates memory unit 6 into one state. However, since at this time the signals to you In the course of the other two counters 4 are absent, the unit state of memory 6 of channel 1 does not affect the operation of the device. With the appearance of the signal at the outputs of counters of channel 2 and 3, a similar signal is formed at the outputs of the majority elements 5, the memory 6 of channel 1 is set to Hj / left state And through the open keys controllable elements 9 and OR 10, a set signal is supplied simultaneously to all three counters. , and thus, the downlink counter k of channel 1 is phased out. In case of consecutive failure of two of the three counters (for definitenethe, we assume that the counters 4 of the channel G and 2 were lost) their phasing occurs as follows (Fig. 2B). Output the signal of the channel 1 counter (fig.). pass through the open element of the barrier 7 (fig. 2B-3), will set the memory unit 6 of channel 1 to one state (fig. 2B-c-). After a certain number of input clocks, the signal is scanned at the output of counter 4 of channel 2 (fig. 2b-c) and in a similar way sets memory block 6 of channel 2 to one state (fig. 2b-n). Switching into memory one unit of memory 6 two channels does not affect the operation of the device as a whole, and only after forming a signal at the output of the counter k of channel 3 (Fig. 2B-d) and translating memory unit 6 into single state ( Fig. 2B-o) of this channel at the output of the coincidence elements 8 (Fig. 2B-K) of all three channels, signals are generated that, having passed through the elements OR 10 (Fig. 2B-Lc), go to the meter installation bus 4, transfer they are in the test state. Signals appear on the outputs of the counters k (Fig. 2B-d, b, 2); a similar signal is formed on the outputs of the majority elements 5 (Fig, 2.B-), the memory blocks 6 are set to zero (fig., K, o) and the keys 9 are opened, through which the installation signal on a single cycle passes to the INPUT of the elements OR 10 (fig. 2B-C) and The one on the tires of the estimator installation (Fig.). Thus, two lost counters are phased out of the third signal. In case of simultaneous failure of two channels to higher states (same), an incorrect signal will be generated at the output, however the probability of such an event is small. Thus, this invention improves the reliability of the device in the event of redundancy of scaling circuits that have a large output asymmetry in the presence of failures. Invention Three-channel-reserved pulsed device containing in each channel a counter, majority element, memory element and prohibition element, is implied by the fact that, in order to increase the reliability of the device, a matching element, key and element are entered into each channel OR, the first input of which is connected to the output of the coincidence element, the second input is connected to the output of the key, and the output is connected to the installation inputs of the counter, the counting of which is connected to the information input of the key, and the output to the information input of the prohibition element and The current inputs of the majority elements of all channels, the output of the majority element of each channel is connected to the control input of the key, to the reset input of the memory element and the prohibitory input of the inhibit element, the output of which is connected to the installation input of the memory element whose output channels. Sources of information taken into account during the examination 1. USSR author's certificate No. 271896, cl. H 05 K 10 / Od, 19692. USSR author's certificate No. 598278, cl. H 05 K 10/00, 1972. 3. USSR author's certificate ff 598278, cl. H-05 K 10/00, 1977 (prototype). FIG.