SU907786A1 - Device for single-side limiting of signal - Google Patents

Description

{54) DEVICE FOR SINGLE-WIDE SIGNAL LIMITATION

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The invention relates to a pulse technique and can be used to generate pulses by limiting, as well as a level lock.

A device for generating pulses by limiting is known, containing four transistors, two of which are interconnected via a common emitter resistor ij

However, this device is characterized by the complexity of the circuit.

A device for limiting a signal is known, comprising a transistor, a load resistor of which is connected to a collector, and a constant voltage source connected between the bins and the emitter, as well as an input source connected between the emitter and the load resistor l, 2j.

However, such a device is characterized by a low quality signal limitation, since it does not allow the generation of pulses with an even tip without a slope.

The closest in technical essence to the invention is a device for one-sided limiting of a signal, also containing a transistor, connected by a collector through a load resistor to one of the poles of the input source, where the collector's collector connection point to the load resistor is the output of the device, and the bias source, setting the limit level connected by the base and the emitter of the 3 J transistor.

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A disadvantage of the known device is the low quality of the signal limitation.

The purpose of the invention is to improve the quality of signal limiting.

The goal is achieved by the fact that in a device for one-sided limitation of a signal containing a transistor connected by a collector through 39 a load resistor to one of the poles of the input source, the junction point of the collector of the transistor with the load resistor is in the output of the device and the bias source specifying the level of the limit connected between the base and the emitter of the transistor, the pole of the input source connected to the load resistor is grounded, the other pole of the source of the input signal is connected A dinene to the base of the transistor is used as a source of bias, which specifies the level of limitation, a current source is used. FIG. I shows a circuit diagram of a device for one-way limiting an electric signal; in fig. 2 - load characteristics on the family of approximated collector characteristics of the transistor; in fig. 3 time diagram of input signal; in fig. 4 is a diagram of the output voltage at the emitter current in FIG. 5 is a timing diagram of the output voltage at the emitter current. The device for one-sided limitation contains a transistor 1, to the collector of which a load resistor 2 is connected, a DC source 3 is connected between its base and the emitter in the forward direction. The device works as follows. If there is an AC input voltage, the following processes occur. During the half-cycle of the input signal with a polarity that coincides with the direction of forward bias, between the base and collector of the transistor (time interval O-t in Fig. 3), the collector current repeats, repeating the shape of the input signal. As a consequence, the form of the voltage across the resistor 2 of the load corresponds to the shape of the input signal. During the half-cycle of the input signal with a polarity corresponding to the reverse bias of the collector-base junction of the transistor between the base and the collector (time tt in Fig. 3} the collector current flows, the amplitude of which depends, u on the current source 3 and the amplitude of the input signal When the source 3 current is set equal to 1cW, the emitter current TK r- flows, in the case of a small amplitude of the input signal UBX corresponding to the diagram a in Fig. 3, the collector current I j does not reach the value of the current of the oscillation (diagram A in Fig. 2) In this The case of limiting the output voltage occurs (plot a. 4). The plot in Fig. 4 illustrates the case where collector current I y reaches the saturation current only at the maximum point of the input signal IR) (plot in Fig. 2 and 3) therefore, the limitation of the output voltage 11 is not yet happening. In cases where the amplitude of the input signal Uny of the boundary value corresponds to the saturation mode of the transistor, the output voltage is limited (plot from Fig. 4). When the current of source 3 changes, the emitter current of the transistor changes and, thus, the threshold of limitation. Thus, as the current of the source 3 increases, the value of the emitter increases to 1. During the half cycle of the input signal with a polarity corresponding to the reverse bias of the collector base transition of the transistor (time interval t - to in Fig. 3) with the input signal that previously exceeded the limitation threshold (diagrams from Fig. 2 and 3), the collector current 1 is no longer reaches the saturation current, and the output voltage kfcix limits occur (plot c in fig. 5). The boundary amplitude of the input signal Ug (plot d in Fig. 2), when the output signal has not yet passed the limit, exceeds its previous value corresponding to 1 (plot in Figs. 2 and 3). And in the case when the amplitude of the input signal i., Causes the trans saturation mode, the output voltage is limited (llgjjj Cepur e (fig3). Thus, when the current of the source 3 is changed, the limit threshold and the amplitude of the output pulses change. The proposed device for one-sided limiting of an electric signal has a high quality of limiting the input signal, since it allows the generation of pulses with a smooth, without slope, peak due to the operating mode of the transistor according to the switching circuit with a common base. In addition, the proposed device, j

compared with the known, has a wider dynamic range.

Claims (3)

Invention Formula A device for unilaterally limiting a signal, comprising a transistor connected by a collector through a load resistor to one of the poles of the input source, the collector junction point of the transistor with the load resistor being the device output, and the bias source specifying the level of the limit connected between the base and the emitter of the transistor, characterized in that, in order to improve the quality of the signal limiting, the input source pole connected to the load resistor is grounded, input source terminal connected to the base of the transistor, and as the bias source zadakedego slice level, a current source is used. Sources of information, taken into account from the expertise one . tTatent of Germany N 1287121, cl. 21 3 36/04, 1969. 2, Stepanenko I, P. Fundamentals of the theory of transistors and transistor circuits. M.-L., Gosenergoizdat, 1963, p. 239, fig. 14-8. 3. Goldenberg L.M. Pulse and digital devices. M., Holy Hour, 1973, p. 206, fig. 5, behind (prototype).