KR800000997Y1 - Vertical deflection circuit - Google Patents

Abstract

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Description

Vertical deflection circuit

1 is a connection diagram showing an example of a conventional vertical deflection circuit.

2 and 3 are waveform diagrams for explaining the operation thereof and hence the operation thereof.

4 is a connection diagram showing an example of a vertical deflection circuit according to the present invention.

5 is a waveform diagram provided to explain the operation thereof.

6 is a connection diagram showing another example of the subject innovation circuit.

The present invention aims to improve the output efficiency with a particularly simple configuration regarding a vertical deflection circuit suitable for application to various television receivers.

In the related art, for example, a vertical deflection circuit in which the output terminal transistor has a SEPP configuration is shown in FIG. This marks the end of the vertical deflection circuit, and a sawtooth drive signal S ₁ synchronous with vertical synchronism is supplied to the input terminal ₂ of the pair of output transistors Q ₁ and Q ₂ of the SEPP circuit, from which both transistor Q _1, a switching to Q _2, and both transistors Q _1, through the capacitor C ₁ from the commonly-connected emitter of Q ₂ (the connection point ℓ ₁₎ by being deflection coil L _D is connected, not to the deflection coil L _D A sawtooth wave signal (current) is generated.

By the way, in the vertical deflection circuit 10 adopting such a configuration, when the emitter voltage of the connection point l ₁ is viewed, the voltage (waveform S ₂ ) of the formulated wave as shown in FIG. 2A is one vertical period. each obtained and, in this case the maximum output signal E is obtained on the emitter of the transistor Q ₁ is a circuit configuration phase, or lower than the power supply voltage E ₀ such as by saturation voltage of the transistor Q _1. Thus, since the drive signal S ₁ having the same sawtooth waveform as the same degree C is supplied to the transistor Q ₁ , the transistor Q ₁ is always turned on during the time points t ₁ to t ₃ when the drive signal S ₁ is supplied.

Therefore, the power consumed by this transistor Q ₁ firstly becomes the voltage wrapped by the oblique line in FIG. 2A, and secondly, the current flowing through the transistor Q ₁ becomes the current wrapped by the oblique line of the same degree B. The power consumption P is the product of the voltage value of FIG. A and the current value of FIG.

However, considering the time point t ₁ to t ₃ at which the power supply voltage E ₀ is supplied from the transistor Q ₁ , the voltage content of the portion (a) (dotted line) enclosed with the voltages E ₀ and E ₀ ′ as shown in FIG. Since it is not a voltage which contributes to an operation relationship but a voltage which is not at all useful, in the conventional vertical deflection circuit 10 as described above, the output efficiency is lowered and the waste of power is increased.

Recently, in order to solve this drawback, a diode was connected in series between the emitters of both transistors Q ₁ and Q ₂ , but even in this case, the emitter voltage waveform becomes the third degree, and at the start of the return, sufficient emitter voltage Is obtained, and the output efficiency is considered to be improved. However, the output efficiency is not much improved since it is clamped to the power supply voltage E ₀ in the middle of the return line.

The present invention aims to improve the output efficiency in consideration of this point, and to simply implement a circuit with a small power consumption.

4, the present invention circuit will be described with reference to the following, and overlapping parts are denoted by the same reference numerals.

In the present invention, the power supply circuit for the SEPP circuit 1 is controlled using the return pulse generated during the return period, and the transistor Q ₁ is driven in the return period at an operating voltage higher than the operating power given to the transistor Q ₁ during the syringe. In this case, the supply of the operating voltages having different voltage values to the transistor Q ₁ in the retrace section and the scan section is performed by the constant voltage circuit 20 described below. In FIG. 4, operation of the SEPP circuit 1 and the input terminal (2) SEPP circuit 1 to the transistor Q ₃ is connected between comprises, but transistor for driving the SEPP circuit (1), this in the first Same as described in FIG.

The constant voltage circuit 20 is connected to m as a power supply of the power supply E connected to the transistor Q ₁ . This constant voltage circuit 20 was obtained using a conventionally known one, and in this example, a series configuration was shown. That is, the control transistor Q ₄ is connected in series to the m by a power supply, the resistor group 21 for comparison voltage generation is connected to the output side of the transistor Q ₄ , and the voltage obtained by the variable resistor 21b therein is a voltage comparison transistor. It is supplied to the base of Q ₅ . The reference voltage generating circuit 24 is constituted by the resistor 22 and the zener diode 23 connected in series, and the control transistor Q ₄ is controlled due to the variation of the output voltage, whereby the output terminal 25 ) To always obtain a constant output voltage E ₀ .

Further, in such a constant voltage circuit 20, the output voltage E ₀ is lower than the input voltage, that is, the power supply voltage E, due to the operation circuit configuration. Although it depends on the circuit constant setting, for example, when the power supply voltage E is 130V, the output voltage E ₀ is about 100V.

In the present invention, the retrace pulse Pr generated in the deflection coil L _D is supplied to the control transistor Q ₄ of the constant voltage circuit 20, and at this time, the deflection coil L is obtained so that an operating voltage different from the normally stable voltage is obtained at the terminal 25. The connection point l ₁ of _D is connected to the base of the control transistor Q ₄ with a series circuit 28 composed of a resistor 26 and a coupling capacitor 27 interposed therebetween.

Although the circuit configuration has been described above, the operation will be described next. For convenience of explanation, the operation will be described at the time point t ₂ shown in FIG. First, as is well known, the retrace pulse Pr generated in the deflection coil L _D is obtained in the retrace period (for the time points t ₂ to t ₂ and the time points t ₄ to t ₅ ), and thus, the retrace pulse Pr is obtained at the time point t ₂ . Can not. Therefore, the constant voltage circuit 20 is given a normal constant voltage characteristic, and a predetermined output voltage E ₀ is obtained to the terminal 25, and in the first half of the scanning time T _S at which the transistor Q ₁ is turned on, The output voltage E ₀ is supplied as the operating voltage of the transistor Q ₁ (see FIG. 5 A). However, since the retrace pulse Pr is generated at the time t ₄ , the retrace pulse Pr is applied to the base of the control transistor Q ₄ through the series circuit 28, so that the base voltage rises, and as a result, the control transistor Q ₄ Since it operates in the forward direction, the output voltage E ₀ of the emitter voltage terminal 25 increases. Ignoring the drop of the voltage V _CE between the collector emitters of the control transistor Q ₄ , the output voltage E ₀ between the supplied time points t ₄ to t ₅ of the return pulse Pr becomes equal to the power supply voltage E, and eventually the transistor Q in the return period Tr. The operating voltage of ₁ becomes the current voltage E. Therefore, the collector voltage of the transistor Q ₁ becomes the voltage waveform S _{4 shown} in FIG. 5A.

In this way, the constant voltage circuit 20 operates normally in the inter-syringe Tr, but the constant voltage circuit 20 does not perform the original constant voltage operation in the retrace period Ts supplied with the retrace pulse Pr. In other words, in the retrace pulse Pr, Since the constant voltage circuit 20 is controlled, the operating voltage of the transistor Q ₁ can also be increased by it only during the return period between the syringes.

Thus, the voltage waveform S ₅ at the connection point l ₁ is applied to the collector of the transistor Q ₁ by supplying the same operating voltage as the waveform S shown in FIG. _5A to the voltage drop due to the resistance of the deflection coil L _D. As shown in FIG. 5B, in this case, the voltage portion of the power consumption P of the transistor Q ₁ becomes the oblique line portion of the solid line shown in FIG. As a result, it is reduced by the portion enclosed by the diagonal lines of the same degree B as compared to the voltage, and as a result, power consumption can be reduced and output efficiency can be improved.

In addition, this circuit features no stable power consumption because these active devices do not use active devices such as semiconductor rectifier devices (GCS, etc.) and diodes related to SEPP configuration. There is a net profit that can be effective and lower the price.

In addition, the output voltage E ₀ obtained at the output terminal 25 is not only provided to the operating voltage of the SEPP circuit 1, but also used as an operating power source for the oscillation circuit shown in FIG. 4 and other video circuits 30 and the like. If it is. In such a case, there is no difference when the operating power source is the output voltage E ₀ , but when the voltage E higher than the output voltage E ₀ is supplied to the terminal 25 as in the present invention, the circuit 30 may be damaged. Therefore, in this invention, the constant voltage circuit 32 which has the zener diode 31 is connected between the terminal 25 and the circuit 30, and the circuit 30 is protected by these.

Further, in this example, the polarity of the sawtooth waveform drive signal S ₁ supplied to the input terminal 2 is selected as in the case of FIG. 1, but the drive of which the polarity of the drive signal S ₁ is inverted in this inlet terminal 2. When the signal S ₁ ′ is supplied, the retrace pulse Pr may be applied to the base of the transistor Q ₅ . In this case it is obtained a voltage waveform of the connection points ₁ ℓ FIG claim 5 is the waveform S ₅ and an inverted state of the B, of course, as in the other wave.

6 shows another example of the present invention, and this example is a case where the constant voltage circuit 20 is modified, and a portion corresponding to the constant voltage circuit 20 of FIG. 4 is attached with a ''. Omit. In this case, the polarity of the driving signal S ₁ applied to the input terminal 2 is the same polarity as in the case of FIG. 4, but the inverted driving signal S ₁ ′ of the polarity is described as the modification of FIG. 4. It is sufficient to apply the retrace pulse Pr to the transistor Q ₅ ′ when supplying to the transistor.

Claims (1)

An operating voltage is supplied to an output terminal transistor of a vertical deflection circuit having a SEPP configuration as described in the text and shown in the text through a constant voltage circuit, and a retrace pulse generated in the deflection coil is applied to the constant voltage circuit, and a return period. The constant deflection circuit is controlled by the retrace pulse, and the output deflection circuit is supplied with an operating voltage higher than that between syringes to improve output efficiency.