SU883771A1 - Device for tolerance frequency monitoring - Google Patents

Description

one

The invention relates to a measuring technique, a mocket used in information-measuring systems for industrial objects.

A device for tolerance control of a frequency, comprising a pulse counter of a controlled frequency, a pulse counter of a reference frequency, a single pulse generator, a comparison unit, two memory blocks and a coincidence element 1, is known.

However, this device does not have sufficient speed and, in addition, difficult.

The closest in technical essence to the present invention is a device for frequency tolerance control, which includes two counters, a reference frequency driver, two triggers, an And element and three indicators 2.

However, the known device is also difficult, in addition, in the frequency range close to the reference, it has low accuracy and speed.

The purpose of the invention is to increase accuracy and speed.

This goal is achieved by the fact that in the device for tolerance control of the frequency, which contains the driver of the reference frequency, two counters, two triggers, the element I and three indicators, the output of the driver of the reference pulse

Frequency 5 is connected to the counter inputs of the counters, the outputs of which are connected to their own interlocking inputs, while the output of the first counter is also connected to the input

10 reset the second counter and the D input of the first trigger, and the output of the second counter is connected to the D input of the second trigger, the C input of which is connected to the input bus, the reset input of the first counter and the C input of the first trigger whose direct output is connected to the first pointer, and the inverse output is connected to one of the inputs of the And element, the output of which is connected to the second pointer, and the other input is connected to the direct output of the second trigger, the inverse output of which is connected to the third pointer.

21 FIG. 1 shows a structural diagram of the proposed device; FIG. 2 - timing diagrams, explaining the principle of operation.

The device contains a driver 1 pulses of the reference frequency.

counters 2 and 3, triggers 4 and 5, item b AND, pointers 7, 8 and 9, and input bus 10.

The device works as follows.

Shaper of the reference frequency generator generates square-wave pulses with a period T. (Fig. 2a), and the selection TO determines the measurement accuracy of the period of the monitored frequency f x / which are fed to the counting inputs of counter 2 with the division factor K 1 and counter 3 with the factor divisions of K 2, with K 1 and K 2 being determined

Td.

K 2 as K 1

K 1,

TO

and T, 2 & more and upper limit T

but valid period values T

controlled frequency.

The signal of the controlled frequency fx nocTynaet, to the reset input of the counter 2 and the counting inputs 0 triggers 4 and 5.

Three cases of operation of the device are possible.

with l

V - -TS

-x lYI KTrfo KTTo

in this case (Fig. 26), the front 1-0 of the first pulse of the controlled frequency f, counter 2 is reset, the logical unit at the output of counter 2 will allow the blocking of counting pulses to enter at its input and, entering the reset input of counter 3, prohibits its operation by setting to its output is the state of a logical unit. This state will continue until. the time T (Fig. 2c), the counter 2 is not set to the saturation state. A logical zero at the output of the counter 2, acting on its blocking input, prohibits the arrival of counting pulses on it and, on entering the reset input of the counter 3, allows its operation. Since the output of the counter 3, and hence the blocking input, was the state of a logical unit, after a time (K 1 + + K 2) -Td relative to the front 1-0 of the first pulse of the monitored frequency fX, counter 3 will also be set to the saturation state (Fig. 2d), the logical zero at the output of the counter 3, entering the blocking input, prohibits the counting pulses from entering it. Thus, by the time the second pulse arrives at the monitored frequency fx, the outputs of counters 2 and 3, and therefore the control inputs of D-flip-flops 4, 5, have a logical zero. The front 0-1 of the second pulse of the controlled frequency f) (on the direct outputs of the D-flip-flops, the state of logical zero is set and the pointer 7 is triggered below, because it has a signal from the inverting output of the D-flip-flop 4. Front 1-0.

The second pulse of the controlled frequency, fx, the counter 2 is reset, the logical unit at its output will permit the input blocking input, the counting pulses to it and reset the counter 3, prohibiting its operation. The loop is repeated.

, ta ,, ±.

in this case, the front 1–0 of the first pulse of the controlled frequency fy, counter 2 is reset, the logical unit at the output of counter 2 will allow the input of the counting pulses to its input and, entering the reset input of the counter 3, prohibits its operation, setting the output of the logical unit at its output , but in the on-state state, the counter 2 is not established, so ak Tj K and the second pulse of the controlled frequency will be reset. Thus, by the time of arrival of the second pulse of the controlled frequency fd, there is a logical unit at the outputs of the counters, and therefore at the control inputs of the D-flip-flops. The front 0-1 of the second pulse of the controlled frequency fx, on the direct outputs of the D-flip-flops, the logical unit will be established and the pointer 9 will work.

Above

since it is fed a signal from the direct output of the D-flip-flop 5.

Front 1-0 of the second pulse of the controlled frequency f; 5, the counter 2 is reset, the logical unit at its output will allow the input of the counting pulses to it at the blocking input and reset the counter 3, prohibiting its operation. Then the cycle repeats.

H

T ,, - r.e-vrrr - v

X .1 x (M + KUT ;,

In this case, the front 1–0 of the first pulse of the controlled frequency, the counter 2 is reset, the logical unit at the output of the counter 2 will allow on its blocking input the arrival of counting pulses on it and, entering the reset input of the counter 3, prohibits its operation, setting its output state logical unit. This state will continue until, after time TQ, the counter 2 is set to the saturation state, the logical zero at the output of the counter 2, entering its blocking input, prohibits the arrival of counting pulses on it and, entering the reset input counter 3, permits its operation, since at the output of counter 5 and therefore at its input the blocking state was a logical one. But in the saturation state, the counter 5 will not be set, since Tp ((K1-K2 Tp

Claims (2)

Thus, by the time of arrival of the second 1-spool of the controlled frequency fy at the output of counter 2, and hence at the control input of D-trigger 5, a logical zero, at the output of counter 3, and therefore at the control input of D-trigger 4 logical unit. The front 0-1 of the second pulse of the controlled frequency at the direct output of D-flip-flop 4 sets a logical unit signal, at the direct output of D-flip-flop 5 a logical zero signal and the pointer 8 Norm trips, since the inputs of element 6 send signals from the direct output of D-flip-flop 4 and inverted output of D-flip-flop 5. Front 1-0 of the second pulse of the controlled frequency f X, counter 2 is reset, the logical unit at its output will allow the input of the counting pulses to it at the blocking input and reset counter 3, prohibiting its operation . Then the cycle repeats. As can be seen from the description of the operation, the device's speed is equal to the period of the controlled frequency f, and the accuracy is determined by the choice of the reference frequency period from the reference frequency driver. Apparatus of the device for tolerance control of a frequency containing a pulse shaper of a reference frequency, two counters, two trigger element And and three pointers, characterized in that, in order to improve accuracy and speed, the output of the pulse shaper of the reference frequency is connected to the counting inputs of the counters, the outputs which are connected to own blocking inputs, while the input of the first counter is also connected to the reset input of the second counter and the D input of the first trigger, and the output of the second counter is connected to the D-in one of the second trigger whose C input is connected to the input bus, the reset input of the first counter and the C input of the first trigger whose direct output is connected to the first pointer, and the inverse output connected to one of the inputs of the And element, the KOTQporo output connected to the second pointer, and the other input is connected to the direct output of the second trigger, the inverse output of which. connected to the third pointer. Sources of information taken into account in the examination 1. USSR author's certificate number 549752, cl. G 01 R 23/00, 1978. 2. USSR author's certificate number 627417, cl. G 01 R 23/00, 1973 (prototype). Kl KZ .... m u IJ iMiniiiiiiiiiiiiNiiiiii K} K2