SU877789A1 - Decoder for series binary codes - Google Patents

Description

one

The invention relates to computing and can be used in digital telemechanics systems for detecting and correcting errors such as transformation or / and erasing characters in a received code pattern.

A decoder for serial binary codes is known, comprising a ring shift register, logic elements and counters l.

The disadvantage of this decoder is its limited scope.

Closest to the proposed is a decoder for serial binary codes, which / contains a ring shift register, each output of which is connected to the input of the element NOT and one of the inputs of the first main element And, the output of the element is NOT connected to one of the input of the second main element And the outputs The main elements AND are connected to the inputs of the main element OR, the output of which is connected to the input of the main pulse counter, two BANNERS, a comparison unit, the first and second outputs of which are connected to the inputs BAN-stand element,

and the second and third outputs - with the inputs of another BAN element, the outputs of the BAN elements are connected to other inputs of the main elements And 2,

If the binary code has the minimum code distance dyy, - (in the sense of Hamming), satisfying the condition + l + l; d; in t + f + l, the known decoder is able to correct t errors such as transformation and 6 errors, a side like erasing characters, and also detect errors like transformation or any number n x 8 + 1 errors like erasing (where n is the value of the code ).

However, the well-known decoder is not able to correct all possible errors such as erasing characters of maximum multiplicity (“comfort.” “Rtitn r, i.e., it does not allow fully implementing the correcting ability of the code.

The purpose of the invention is to improve the noise immunity of the decoder.

The goal is achieved by the fact that the decoder contains an additional pulse counter, additional elements AND, additional elements OR, the input of an additional pulse counter connected to the second. 30. The output of the comparison unit, the first output of the additional pulse counter is connected to the first inputs of one additional AND elements, the second inputs of which are connected to the second outputs of the main pulse counters, and the second output of the additional pulse counter - to the first inputs of other additional And elements, the second inputs of which connected to the first outputs of the main pulse counters, the outputs of each pair of additional elements And, the inputs of which are connected to the first and second outputs of the same main account ika pulses are connected to the inputs of OR additional elements.

The drawing shows a schematic diagram of the proposed decoder for serial binary codes.

The device contains a circular register 1 shift, block 2 comparison, the elements of the prohibition 3, 4 with the prohibitory input X, an additional counter 5 pulses, additional elements AND and additional elements OR, elements NOT, main elements AND IQj -Y, basic elements OR and main counters (d pulses.

The decoder works as follows.

If in the received code combination. contains the number of erase characters, not equal to 1 yy, the decoder works in the same way as the well-known decoder, i.e. the signals at its output will be determined by signals from the second outputs t of the main counters 12 12 | y (for pulses arriving at the inputs of additional elements And 7 / l which are opened by the second inputs with a signal from the first output of tyy 5 (additional counter 5 pulses the output of the main pulse counter takes place only if t pulses have arrived at its input, and the signal at the first output of the additional pulse counter - only when a number of pulses not equal to it arrives at its input block and 2 comparisons, on which the reception of erasure symbols X is fixed. The reception of the zero value of the symbol is fixed at the first output O, and the reception of a single value at the third output 1 of the comparison block 2. The first and third outputs of the comparison block 2 are connected to the information inputs of the BANNER 3 elements and 4, and the second output of the comparison block - with prohibiting inputs of the BAN 3. and 4 elements.

In the case when the number of erase characters in the code combination is equal to the output, the signals at the output of the decoder will be determined by the signals from the first outputs O of the main counters of 12-12 signals pulses received at the inputs of additional elements And

. which are open on the second inputs by the signal from the second output

F "h" g tt C

counter 5,

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The signal at the first output of the main counter takes place only in its zero state, when not a single pulse has arrived at the counter input, and the signal at the second output of the additional pulse counter — only when 1 д dx °° d niH-l arrives at its input pulses with Btoporo output X block 2 comparison. In this case, the erase characters will be corrected if there were no other distortions in the code combination. If, along with the erased symbols, there will be distortions of the type of transformation of symbols, then a protective failure will be provided in the decoder, since the outputs O of all the main counters 12., -. 12m pulse signals will be absent.

Claims (2)

Invention Formula Decoder for serial binary codes containing a ring shift register, each output of which is connected to the input of the YE element and one of the inputs of the first main element AND, the output of the element is NOT connected to one of the Biioporo inputs of the main element AND, the outputs of the main AND elements are connected to the inputs of the main element OR , the output of which is connected to the input of the main pulse counter, two BANKS, the comparison unit, the first and second outputs of which are connected to the inputs of one BAN, and the second and third outputs - with I With the signals of the other BANNER element, the outputs of the BAN elements are connected to each other by the inputs of the main elements AND, which differ. so that, in order to increase the resistance of the decoder, it contains an additional pulse counter, additional AND elements, additional OR elements, an additional pulse counter input is connected to the second output of the comparator unit, the first output of the additional pulse counter is connected to the first inputs of one additional AND elements, the second inputs of which are connected to the second outputs of the main pulse counters and the second output of the additional pulse counter - with the first inputs of other additional elec ENTOV And, the second inputs of which are connected with the first main schetchikbv outputs pulses, the outputs of each pair of additional AND gates whose inputs are connected to first and second outputs of the same main pulse counter connected to the inputs of OR additional elements. Sources of information taken into account in the examination li USSR Author's Certificate (227707, class, H 03 K 23/00, 1968. 2. F.E. Graphs coding and decoding device. M., Energie, 1972, p. 92 (prototype).