SU873275A1 - Memory - Google Patents

Description

(54) STORAGE DEVICE

I

The invention relates to computing and can be used in digital computing machines (digital computers) and automation devices.

A memory device (memory) containing a drive, address register, decoder, X and Y coordinate keys, weak signal output amplifiers with gating from a common gate driver p.

This storage device is less noise-resistant and reliable than other similar storage devices due to the presence of interference in phase with the desired signal and the complexity of storage and output amplifiers. To distinguish between output signals O and 1, amplitude and time selectors, threshold circuits, and special gating circuits have to be used, however, this complicates the design of the device, especially the operating circuit. so in a wide range of mechanical-. climatic and climatic influences. ,

The closest technical solution to the proposed is a memory device containing the address register, one of the inputs of which is connected to the code bus Installation. Oh, other inputs - to the address code bus, and the outputs are connected respectively to the inputs of the decoder and the address current driver, the corresponding driver input

10 address currents are connected to one of the code buses, and the outputs are connected to the accumulator inputs, read amplifiers, one inputs of which are connected to the gate driver inputs and the block

15 controls iZj.

However, in this device, due to the presence of parasitic inductances and capacitances, as well as power supply noise, the input signal O represents so20 no impulse, but a pulse in phase with the useful signal 1, which can lead to a false positive — fixing the signal I instead

ABOUT

Similar to signal

Qi can occur both in RAM and a transformer type ROM with direct firmware (when writing O leads the ferrite core when writing), in which the most significant interference is due to the presence of parasitic capacitances and inductances between the piercing wires. The presence of these I noise significantly impairs the noise-resistant transformer ROM, and therefore their reliability

The purpose of the invention is to increase the reliability of the device due to interference suppression and phase difference, 1x O and 1 signals.

The goal is achieved by the fact that an additional address current driver, an additional accumulator delay block, a trigger trigger, a block of AND elements, an OR element, AND elements are entered into the memory, the inputs of the first AND element are connected to the corresponding code buses, the output of the first AND element is connected to the input trigger trigger, the first and second outputs of which are connected respectively to the first inputs of the second and third elements AND, the second inputs of which are connected to one output of the delay unit, the other outputs The ports of which are connected to the first inputs of the I block, the second inputs of which are connected to one of the decoder outputs, the other output of the decoder and the output of the second element AND are connected to the corresponding inputs of the additional address current generator, the output of which is connected to one of the additional accumulator inputs of the third And element and block 5.Pments and are connected to the inputs of the zemnevta OR, the output of which is connected to the input of the strobe driver, the outputs of the SS storage device are connected to other inputs of the additional accumulator The module, whose outputs are connected to other inputs of the read amplifier, the outputs of the control unit are connected to the corresponding input of the additional address current generator.

The drawing shows a block diagram of the device memory.

The memory device contains the address register I, the driver 2 address currents, the accumulator 3, the read amplifier 4, the driver

; 5 strobe; additional storage device 6 and driver of address current 7, control unit 8, decoder 9, trigger trigger 10, delay unit 1I,

block of 12 elements And, elements 13-15 And, element 16 OR.

The operation of this storage device is significantly different from that known when reading information.

from the storage device, since it is not only polled in this device. line of numbers at the selected address in drive 3 using register 1 and driver 2, but also. an additional accumulator 6 using an additional driver 7 and a decoder 9. The received output signals are summed at the output bit buses, and the signals o and 1, which differ in phase, are received at the inputs of the read amplifier 4. This greatly simplifies the selection of output signals, increases the noise immunity of the amplifier 4 and reliability

storage device.

In the read mode from other digital computer devices, the code bus receives the signals of the address code, Run, Installation. Inclusion of additional storage device. The Set O signal prepares the register 1 triggers and initializes the trigger 10 of the additional accumulator 6. The address code signals through the address register go to the decoder and driver 2 address currents, and the Start signal in the selected line of the accumulator 3 runs the polling current Formation of output signals O and 1 in the output tires. These signals can significantly increase due to interference. differ from each other, making it difficult to distinguish them reliably. In the case of a signal coming from the code bus, the inclusion of the additional storage signal, the Start also through the first element 13, triggers the trigger 10 for the start of the additional storage 6 and. enters the block 11 of the delay 11. Through the block 11 and elementa.nt 14 And on the signal of the resolution from the trigger 10 the delayed signal Run starts an additional driver 7 s

Claims (2)

5 by the time delay determined by the decoder 9. The amplitude and the front of the polling current of the additional accumulator 6, coming from the driver 5 l 7, is regulated with. using the control unit 8 (according to the amplitude of the current and the front of the current pulse, the amplitude of the additional output signals in bits of ton is determined). The current in the accumulator 6 from the former 7 is selected so that the output signals from the accumulator 6 in the discharge / buses be opposite to signal 1 /. In drive 6, the same information is recorded in all bits (for example, all 1). As a result of the survey of the numerical ruler in the accumulator 3 and the additional numerical ruler on the accumulator 6 in the bit buses, two signals are formed, which are algebraically combined. At the same time, the output signals I of the number line of the accumulator 3 decrease somewhat in amplitude, and the output signals O become opposite in phase. The location and amplitude of the additional output signals is determined by the decoder 9 and the control unit 8. The start of the gate generator 5 is automatically determined by the location of the additional signal from the decoder 9 and the signal from the delay unit 11 through elements 12 AND and element 16 OR. Such a start of the gate driver is necessary due to the resulting shift of output signals O and 1 when they are summed up with the signals of additional number line of accumulator 6, in the absence of a signal, the additional accumulator is switched on, the interrogator of the additional accumulator does not work, and the gate former is started by element 15 AND according to the enable signal from trigger 10, which is in this case in the zero state. Thus, by selecting the required amplitude and duration of the polling current of the numerical scale in the additional accumulator 6, it is possible to provide the specified parameters of the output signals 1 and O at the input of the read amplifier. The use of this memory device allows to suppress the arising interference and to obtain the phase difference of the signals O and 1. Therefore, the read amplifier circuits are considerably simplified and the limits of the device operability under climatic and mechanical influences and changes in the supply voltage are extended. Claims of the invention A memory device containing an address register, one of the inputs of which is connected to a code bus. Installation O, the other inputs - to the code address bus, and the outputs are connected respectively to the decryption inputs. torrent and address current driver j. The corresponding input of the address current driver is connected to one of the code buses, and the outputs are connected to the accumulator inputs, a read amplifier, whose inputs are connected to the strobe single-circuit inputs and the control unit, different in that reliability of the storage device, an additional drive, an additional address current driver, a backup unit, a start trigger, a block of AND elements, an OR element, AND elements, are entered into it, with the inputs of the first AND element Connected to the corresponding code bus, the output of the first element I is connected to the trigger trigger input, the first and second gates of which are connected respectively to the first inputs of the second and third And elements, the second inputs are connected to the back outputs of the delay unit, the other outputs of which are connected to the first hoops And elements, the second inputs of which are connected to one of the outputs of the peshifratope, another output of the descrambler and the output of the second element And are connected to the corresponding inputs of the additional Shaper of address currents, the stroke of which is connected to one of the inputs of the additional accumulator, the outputs of the rubbing of the AND element and the block of the elements AND are connected to the inputs of the OR element, the output of which is connected to the INPUT of the stomorative drive. -; Ladies of the read amplifier, the outputs of the control unit on; | are connected to the corresponding input of the additional formator of address currents. Sources of information taken into account in the examination. Brik E. A. Technique of permanent storage devices. M., Soviet Radio, 1975, p. Ii. 2. Shigin A. G., Deryugin A. A. Digital computers. M., Energie, 1975, p. 74 (prototype).