SU871054A1 - Eddy current flaw detector for checking lengthy articles - Google Patents

Description

The invention relates to non-destructive testing and can be used for flaw detection of extended products. The eddy current flaw detector is known, which contains a sequential signal generator, an eddy current transducer, a signal processing unit, a defect recognition unit, a length-code transducer whose output is connected to the input of the incrementing device, and the tl3 indicator. A disadvantage of this device is the low defect position determination accuracy. The closest to the invention in its technical nature is an eddy current flaw detector for controlling manufactured products, containing a generator connected in series, a vortex current transducer, a signal processing unit and an oscilloscope connected to its outputs and an L2 indicator. A significant disadvantage of this flaw detector is the inability to determine the coordinates and length of each defect. This is especially important for longitudinal products such as wire, tape, supplied in riots and coils several hundred meters long and even tens of kilometers. In this case, it is necessary to know not only the total length of the defective areas, but in which area the defect started and where it ended. By controlling the wire cutting mechanisms, it is possible not to send defective areas in a further period. The aim of the invention is to determine the coordinates of the defect on the monitored product. The goal is achieved by the fact that the flaw detector is equipped with two memory blocks, an AND circuit, the output of which is connected to the memory control inputs, connected by a program block, the reference input of which is connected to the generator output, an N-bit counter, the outputs of which are connected to the inputs of the memory blocks and the AND circuit, the buffer block, the informative inputs of which are connected to the outputs of the pgiadti block, and the control block, the output - with the control input of the program block, and the digital printing block., as well as the blocking circuit, output cat The link is connected to the control unit of the program block and two memory blocks connected in parallel.

length-code converter, the output of which is connected to the inputs of the signal processing unit and the software block and the recognition circuit of the beginning and end of the defect, the inputs of which are connected to the outputs of the length-code converter and the signal processing block, and the outputs with the memory enablers.

The drawing shows the block diagram of the proposed flaw detector. It contains a generator 1 connected in series, an eddy current converter 2, a signal processing unit 3 and an oscilloscope 4 connected to its outputs 4 and an indicator 5, and two memory blocks 6 and 7, an AND 8 circuit, whose output is connected to the control inputs b and 7 These are connected in series by software block 9, the reference input of which is connected to the output of generator 1, .N-bit counter 10, the outputs of which are connected to the inputs of blocks 6 and 7 of memory and circuit AND 8, the buffer block 11, whose informative inputs are connected to the outputs of blocks 6 and 7, and the control output output - with the control input of software block 9, and digit printing block 12, as well as blocking circuit 13, the output of which is connected to the control inputs nporpsiMmnogo block 9 and two blocks b and 7 of memory, connected in parallel, converter length-code, output of which is connected to the entrances. signal processing unit 3 and software unit 9, and a start and end defect detection circuit 15, the inputs of which are connected to the outputs of the length-code converter 14 and the signal processing unit 3, and the outputs to the resolution inputs of blocks b and 7 of memory.

The flaw detector works as follows.

The signals of the eddy current transducer 2, excited by generator 1, are fed to the signal processing unit 3 where they are processed according to a predetermined algorithm (amplitude-phase, frequency selection, etc.). From the processing unit 3, the signals are first fed to the oscilloscope 4 and the indicator 5 to determine the total length of the object, and to determine the coordinate of the defect to the input of the circuit 15 recognizing the beginning and end of the defect. The same circuit receives the clock pulses from the Converter 14 length-code. The start and end defect recognition circuit 15 has two outputs: the start and exit ends of the defect end. Circuit 15 contains a two-bit shift register (not shown), information in which is advanced by clock pulses of the transducer 14. The beginning of the defect corresponds to the combination 01, recorded in the shift register of the circuit 15, when the defect signal arrives in the intervals between the cycles. If the length of the defect / is greater than the distance of one cycle, combination 11 will appear in the shift register of circuit 15 at the end of defect 10. Ha4aj: J of operation (no defect) corresponds to combination 00.

Thus, at the outputs of circuit 15, signals of start and end of the defect are present, which are permissive for selecting one of the cells in blocks b and 7 of memory.

The control inputs of the memory blocks 6 and 7 also receive signals from the blocking circuit 13 from the presence of the product. The arrival of these signals ensures that the unit is written to the memory location. The cell selection is performed by the value of the number recorded in the N-bit counter 10, which, when checking the product, performs a continuous counting of clock pulses at its input through program block 9 from the output of the length-code converter 14. In this case, the clock signals are passed to the output of the program block 9 only if there is a signal at the corresponding input of this block that there is a product coming from the blocking circuit 13. Thus, writing to blocks b and 7 of memory occurs at the time of the arrival of the enabling signals of the beginning and end of the defect.

After the end of control, the product leaves the eddy current transducer 2, and at the output of blocking block 13, the signal of the presence of the product disappears. The software block 9 sets the N-bit counter 10 to zero, prohibits the passage of clock pulses from the length-code converter 14 and allows the pulse generator from the generator 1 to arrive at the N-bit counter 10. A pulse of a given amplitude and duty ratio is generated. In the software block 9, the N-bit counter 10 counts the number of pulses from generator 1, and at the inputs — resolving, recording and erasing — a combination of signals is generated, decisive reading of information from blocks b and 7 of memory. When such a combination of numbers appears on the N-bit counter that occurred when recording information about the product defectiveness, the output of blocks b and 7 of the memory sends output signals that are sent to the digital printing block 12 via the buffer unit 11. The same signals will allow the information accumulated in the N-bit counter to enter through the buffer unit 11 to the block 12 for digital printing.

Claims (2)

In order to provide the time required for digital printing, a delay of the passage of counting pulses to the N-bit counter is provided, which is carried out by feedback between the (n + 3) th output of the buffer unit 11 and the control input of the programmable unit 9. After the completion of the drawdown, the counting continues until the following signals appear in blocks 6 and 7 of the memory, etc., until the N-bit counter is completely filled. When all the N-square cells of the counter are filled, the output of the AND 8 circuit will be with inputs on vitsggsh, erasing recorded in b 6 and 7 Okahim memory information .. The flaw detector is driven to the original position / suitable for controlling the following of Delhi. DETAILED DESCRIPTION OF THE INVENTION Claims Eddy current flaw detector for monitoring extended products, containing a generator connected in series, an eddy current transducer, a signal processing unit and an oscilloscope and an indicator connected to its outputs, characterized in that, in order to determine the coordinates of a defect on a monitored product, In this case, the AND circuit, the output of which is connected to the inputs of the control of memory blocks connected in series by a programmable block, the reference input of which is connected to the output of the generator, is N-bit a counter, the outputs of which are connected to the inputs of the memory block and the AND circuit, the buffer block, the informational inputs of which are connected to the outputs of the memory block and the control output of the control block of the program block, and the digital printing block, and the blocking circuit, output which is connected to the onboard pair of control inputs of the software unit and two memory blocks, a length-code converter, the output of which is connected to the inputs of the signal processing unit and the program block, and a recognition circuit of the beginning and end of the defect, the inputs which are connected to the outputs of the length-code converter and the signal processing unit, and the outputs to the inputs of the resolution of the memory blocks. Sources of information taken into account in the examination 1. Patent IT 3475681, cl. 01 N 27/86, 1973. 2. Author's certificate of the USSR 557310, class. With 01 N 27/86, 1975 (prototype).