SU869029A1 - Bipolar-to-single polar code converter - Google Patents

Description

They are connected to the output of one of the corresponding AND-NOT elements of the third and fourth groups, and the first inputs of the IS-NOT elements in each of the third and fourth groups are interconnected and connected respectively to the third and fourth inputs of the logic unit, the additional inputs of which are connected to the second inputs of the elements AND-NOT the third and fourth groups.

The drawing shows a structural electrical circuit for converting a bipolar code into a unipolar code.

The converter contains two channels, the first of which consists of a voltage divider 1, a limiting amplifier 2, an amplifier 3, and a signal level converter 4, and the second from a voltage divider 5, a amplifier limiting 6, amplifier 7 and a signal level converter 8 , and logic block 9, which contains eight AND-HE elements 10-17 and three OR elements 18-20, control signal buses 21 and 22, input tires 23 and 24, output buses 25-27.

The device works as follows.

In the absence of an input signal, there is a zero potential on the input buses 23 and 24, while the outputs of the limiters 2 and b have a high logic level. ,

At the outputs of amplifiers 3 and 7 there is a negative potential, which is converted by converters 4 and 8 of the signal level to a high logic level at their outputs. The control signal buses 21 and 22 also have a high logic level. At the same time, at the outputs of the AND-NE elements 10-13 there is a low logic level, at the outputs of the AND-NOT elements 14-17 - a high logic level, at all outputs of the bipolar code converter (at the outputs of all the OR elements) low logic levels.

When a signal of unit information appears, the positive potential at the first input and the negative potential at the second input correspond, a low logic level appears at the output of limiting amplifier 2, and the negative potential at the amplifier output decreases and converts the converter 8 to a low logic level his exit. The state of the amplifier limiter 6, the amplifier 3 and the level 4 converter does not change. Low logic levels at the inputs of the AND-HEY elements 10 and 13 result in the appearance of high logic levels at their outputs. The coincidence of high logic levels at the inputs of the AND-HEY element 14 leads to the appearance of a low logic level at its output, while on the buses 25 and 26 of the elements OR 18 and 19 there are high logic levels, unit information signals and a clock pulse.

When a signal of zero information appears, the negative potential on the first bus 23 and the positive potential on the second 2 correspond to a low logic level at the outputs of the limiter amplifier 6 and the 4-level converter. The state of the limiter amplifier b and the level 8 converter does not change. As a result, the outputs of the AND-NE elements 11 and 12 appear high logic levels, their coincidence at the input of the sixth AND-NOT element 15 leads to the appearance of a low logic level at the second input. the element OR 19 and to its appearance on the output bus 26 of a high logic level, a clock pulse signal. On the output bus 25, the logic level remains low, the information signal is zero.

When a noise appears, the same potentials on buses 23 and 24 correspond to the same, low logic potentials appear at the outputs of limiting amplifiers 2 and 6 (at positive input potentials) or at the outputs of transfer elements of converters 4 and 8 damage (at negative input signals), which leads to the coincidence of high logic levels at the inputs of the AND-NOT elements 16 and 17, to the appearance of a low logic level at the input of the element OR 20 and a high logic level on its output bus 27 of the fault signal.

The appearance of a signal in only one of the channels does not lead to the appearance of an output signal, since the inputs of the corresponding IS-NOT element from 14 to 17 do not have the same two high logic levels. If the busses 21 and 22 are supplied with a low logic level, then, at the outputs, the elements of IS-NE 10 and 15 or 1.2 and 13, respectively, a high logic level appears that allows the passage of a signal from another channel. At the same time, the output signals are accompanied by a fault signal indicating that the information is incomplete.

Thus, the proposed converter of the bipolar code into unipolar allows for the billing of information when the conditions for its transmission deteriorate. When the useful signal overlaps with a noise signal, a signal is received, according to which, although with reduced reliability, it is possible to partially recover information that in other similar

devices are simply cut out or, in some cases, skipped without indicating unreliability. The converter makes it possible to fully utilize the redundancy incorporated in the bipolar code and ensures the reception of information even when one of the channels goes out of order.

Claims (2)

1. Bipolar-to-unipolar code converter, containing two voltage dividers, each input and connected to one of the input buses, and the output through the appropriate amplifier-limiter connected to one of the inputs of the logic unit, the third and fourth inputs of which are connected to the tires a control signal, characterized in that, in order to increase the reliability of the conversion, two signal level converters and two amplifiers are introduced into it, the input of each of which is connected to the output of one of the voltage dividers, and the output through otvetstvuk tions signal level converter is connected to an additional input of the logic block. 2. The converter according to claim 1, characterized in that the logic block contains eight AND-NOT elements grouped in groups of two and three OR elements, the inputs of the first two of which are connected to the outputs of the AND-elements of the first group, the inputs of the third connected to the outputs of the elements and IS NOT the second group, and O each input of the AND-.NE elements of the first group is connected to one of the inputs of the NAND elements of the second group and connected to the output of one of the corresponding elements of the third AND 4, vertical groups, and the first inputs of the AND-N elements in each of the third and fourth groups interconnected and connected respectively to the third and fourth inputs of the logic unit, the additional inputs of which are connected to the second inputs of the elements of the third and fourth groups of the NAND, Sources of information taken into account in the examination 1. US Patent 3,139,615, 5 cl. 340-347, 08.06.64. 2, USSR author's certificate  658735, class H 03 K 13/24, 30.12.76.