SU866770A1

SU866770A1 - Synchronizing device

Info

Publication number: SU866770A1
Application number: SU792863718A
Authority: SU
Inventors: Евгений Алексеевич Ефимов; Алексей Яковлевич Титов
Original assignee: Предприятие П/Я Г-4190
Priority date: 1979-12-26
Filing date: 1979-12-26
Publication date: 1981-09-23

Description

Изобретение относится к радиотехнике й может использоваться для поиска и син-¹хронизании сложных сигналов.The invention relates to a radio minutes can be used to search for and syn- ¹ hronizanii complex signals.

Известно устройство синхронизации, содержащее согласованный фильтр, детектор,, пороговый блок и блок управления вхожде- $ нием в синхронизм, а также последовательно соединенные генератор тактовых импульсов и делитель [1].A synchronization device is known that contains a matched filter, a detector, a threshold unit and a control unit for entering synchronism, as well as a series-connected clock generator and divider [1].

Однако известное устройство требует затраты значительного времени вхождения в синхронизм и не обеспечивает достаточной точности обнаружения сигнала.However, the known device requires a significant time to enter synchronism and does not provide sufficient accuracy of signal detection.

Цель изобретения - сокращение времени вхождения в синхронизм и повышение точности обнаружения сигнала.The purpose of the invention is to reduce the time of entry into synchronism and increase the accuracy of signal detection.

Для достижения поставленной цели в известное устройство синхронизации введены последовательно соединенные счетчик адреса фазы, блок оперативной памяти и блок Анализа, первый и второй выходы которого подключены соответственно к второму входу блока оперативной памяти и входу блока управления вхождением в син2 хронизм, выход которого подключен к второму входу блока анализа и входу согласованного фильтра, выход которого через последовательно соединенные детектор..и пороговый блок подключены к третьему входу блока анализа, при этом выход генератора тактовых импульсов подключен к третьему входу блока оперативной памяти, а выход делителя - к входу счетчика адреса фазы.To achieve this goal, a phase counter, a RAM block and an Analysis block are introduced in series into the known synchronization device, the first and second outputs of which are connected respectively to the second input of the RAM block and the input of the sync chronometer control input, the output of which is connected to the second input the analysis unit and the input of the matched filter, the output of which is through a series-connected detector .. and the threshold unit is connected to the third input of the analysis unit, while the output the clock generator is connected to the third input of the RAM block, and the output of the divider is connected to the input of the phase address counter.

На чертеже представлена структурная .электрическая схема предложенного устройства.The drawing shows a structural. Electrical diagram of the proposed device.

Устройство синхронизации содержит согласованный фильтр 1, детектор 2, пороговый блок 3, блок 4 анализа, блок 5 оперативной памяти, счетчик 6 адреса фазы, блок 7 управления вхождением в синхронизм, генератор 8 тактовых импульсов и делитель 9.The synchronization device contains a matched filter 1, detector 2, threshold block 3, analysis block 4, random access memory block 5, phase address counter 6, synchronization entry control unit 7, clock generator 8 and a divider 9.

Устройство работает следующим образом.The device operates as follows.

На вход порогового блока 3 поступает напряжение с еыходэ согласованного фильтра 1 через детектор 2.The input of the threshold unit 3 receives voltage from the output of the matched filter 1 through detector 2.

Блок 4 производит.суммирование части пересечений и вычитание числа непересечений напряжения с выхода детектора 2 периодически повторяющихся элементарных интервалов.Block 4 performs the summation of part of the intersections and subtraction of the number of voltage non-intersections from the output of the detector 2 of periodically repeating elementary intervals.

В течение первого периода поиска фазы входного сигнала блок 4 устанавливается в начальное состояние, которое заносится по всем адресам в блок 5. В последующие периоды поиска фазы входного сигнала из блока 5 по импульсам от генератора 8 выбирается предыдущее значение анализа, записывается в блок 4 производится анализ и результат по тому же адресу заносится в ОЗУ блока 4, так как на счетчик 6 поступают импульсы через делитель 9. Елок 7 анализирует состояние реверсивного счетчика блока 4 и в случае достижения верхней границы вероятности выдает сигнал обнаружения, т.е. в данный момент фаза входного и опорного сигналов совпадают.During the first period of searching for the phase of the input signal, block 4 is set to the initial state, which is entered at all addresses in block 5. In subsequent periods of searching for the phase of the input signal from block 5, the previous analysis value is selected by pulses from generator 8, and recorded in block 4, the analysis is performed and the result at the same address is entered in the RAM of block 4, since pulses are sent to counter 6 through a divider 9. Elok 7 analyzes the status of the reverse counter of block 4 and, if the upper limit of probability is reached, gives nal detection, i.e. at the moment, the phase of the input and reference signals are the same.

Если та передающая станина, с которой, возможна связь по приему, не работает, т.е. не передается информационный сложный сигнал из ансамбля входных сигналов, то на вход порогового блока 3 поступает модуль огибающей функции взаимной корреляции опорного сигнала и шума. Таким образом, во всех элементарных интервалах происходит превышение порогового значения с вероятностью . В случае достижения нижней границы в 1 -ом элементарном интервале анализ в нем прекращается и производится рециркуляция кода, соответствующего нижней границе. При достижении нижней границы во всех элементарных интервалах блок 7 устанавливает блок 4 в исходное состояние и выдает сигнал перестройки согласованΙηογο фильтра 1, после чего повторяется весь цикл поиска.If the transmitting bed with which reception is possible does not work, i.e. if an informational complex signal is not transmitted from the ensemble of input signals, then the envelope module of the mutual correlation function of the reference signal and noise is fed to the input of the threshold block 3. Thus, in all elementary intervals, the threshold value is exceeded with probability. If the lower limit is reached in the 1st elementary interval, the analysis in it stops and the code corresponding to the lower boundary is recycled. Upon reaching the lower limit in all elementary intervals, block 7 sets block 4 to its initial state and generates a tuning signal matched to filter 1, then the entire search cycle is repeated.

Метод последовательного анализа одновременно во всех элементарных интервалах, примененный в устройстве для поиска основного корреляционного пика,повышает помехоустойчивость устройства по входу. Таким образом, применение предлагаемого изобретения в приемнике приводит к возможности понижения необходимой излучаемой мощности передатчика.The method of sequential analysis simultaneously in all elementary intervals, used in the device to search for the main correlation peak, increases the noise immunity of the device at the input. Thus, the application of the invention in the receiver leads to the possibility of lowering the required radiated power of the transmitter.

Claims

The invention relates to radio engineering and can be used to search and synchronize complex signals. A synchronization device is known that contains a matching filter, a detector, a threshold unit and a synchrophase acquisition unit, as well as serially connected clock generator and divider l) However, the known device requires a considerable amount of time to become synchronized and does not provide sufficient accuracy in signal detection. The purpose of the invention is to reduce the time of entry into synchronism and increase the accuracy of signal detection. In order to achieve this goal, a phase connected address counter, a RAM unit and a front end unit are entered into a known synchronization device, the first and second outputs of which are connected respectively to the second input of the main memory unit and the input of the synchrometer control unit whose output is connected to the second the input of the analysis unit and the input of the matched filter, the output of which is connected to the third stage of the analysis unit through series-connected detectors and threshold unit; The clock generator is connected to the third input of the RAM, and the divider output is connected to the input of the phase address counter. The drawing shows a structural electrical circuit of the proposed device. The synchronization device contains a matched filter 1, detector 2, threshold unit 3, analysis unit 4, main memory unit 5, phase address counter 6, synchronization acquisition unit 7, clock pulse generator 8 and divider 9. The device operates as follows. The input of the pulverized unit 3 receives the voltage from the output of the matched filter 1 through the detector

2. Block 4 produces, summing up part of the intersections and subtracting the number of voltage non-intersections from the output of detector 2 of periodically repeated elementary intervals. During the first period of the search phase of the input signal, block 4 is set to the initial state, which is entered at all addresses in block 5. In the subsequent periods of the search for the phase of the input signal from block 5, the previous analysis value is selected by pulses from generator 8, recorded in block 4 analysis is performed and the result at the same address is entered into the RAM of block 4, since counter 6 receives pulses through divider 9, Block 7 analyzes the state of the reverse counter of block 4 and in case of reaching the upper limit of probability gives detection signal, i.e. at the moment of interest, the phase of the input and reference signals coincide. If the transmitting bed with which the communication is possible by reception does not work, i.e. the information complex signal is not transmitted from the ensemble of input signals, then the envelope of the function of the mutual correlation of the reference signal and noise enters the input of the threshold unit 3. Thus, in all elementary interlaces, the threshold value is exceeded with probability C. If the lower bound is reached in the 1 st eLEmental interval, the analysis in it is stopped and a code is recirculated that corresponds to the lower limit. When the lower limit is reached in all elementary intervals, block 7 sets block 4 to the initial state and issues a tuning signal that is passed by 8 04 HOro filter 1, after which the entire search cycle is repeated. The method of sequential analysis simultaneously in all elementary intervals, applied in the device to search for the main correlation peak, increases the noise immunity of the device at the input. Thus, the application of the invention in the receiver leads to the possibility of reducing the required radiated power of the transmitter. Formula Fig. 1. A synchronization device comprising a matched filter, a detector, a threshold block and a block, synchronization acquisition control, as well as serially connected clock generator and a divider, characterized in that, in order to reduce synchronization time and increase Accuracy of detection of the signal, the phase address counter connected in series, the RAM block and the analysis block are entered, the first and second outputs of which are connected respectively to the second input of the RAM block and the input of the synchronization control unit, the output of which is connected to the second input of the analysis unit and the input of the matched filter, the output of which is connected through the serially connected detector and threshold unit to the third input of the analysis unit, while the output of the clock generator is connected to the third input of the operational unit memory, and the output of the divider is connected to the input of the counter adress phase. Sources of information taken into account in the examination 1. Copyright certificate № 464981, cl. H 04 L 7/02, 1974 (prototype).

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