SU851403A1 - Device for substruction - Google Patents

Description

(54) DEVICE FOR HEATING

The invention relates to computing and is intended to subtract two binary numbers. A subtractor is known which contains two registers, a single-charge adder for three inputs and two flip-flops 1. A disadvantage of this device is the complexity of its implementation. It is also known a subtraction device comprising two registers and a trigger, the unit output of which is connected to the first input of the first element AND, zero output — to the first input of the second element AND, the single input — to the output of the first delay element connected to the input and output of the second element AND , the second input, which is connected to the second input of the first element And and the output of the first register connected by the input to the output of the first element And the output of the second register is connected to the first input of the third element And and to the input of the investment torus, the output of which is connected to the first input of the fourth element AND, connected by the output to the first input of the first element OR, the second input of which is connected to the output of the third legit, and the output to the input of the second register, the zero output of the trigger is connected to the second input of the third element And, single output - with the second input of the fourth element AND, zero input - with the output of the second delay element, the input of which is connected to the output of the second OR element, / connected by the first input to the output of the second register and the second input to the bus sa T2. . A disadvantage of this subtractor is a relatively large number of logic elements. Closest to the present invention is a subtraction device containing two registers and a trigger connected by a single output to the first input of the first AND element, a zero output to the first input of the second AND element, a single input through the first delay element with the output of the second And element, the second input which is connected to the second input of the first element AND and the output of the first register connected by the input to the output of the first element AND, and the input of the second register is connected to the output of the first element OR;

the first input of which is connected to the output of the third OE terminal AND connected by the first input to the output of the second register and the first input of the second OR element, the second input of which is connected to the reset bus, the single trigger input is connected to the second input of the first OR element, the zero output of the trigger is connected through the second the delay element with the second input of the third element And, the zero input of the trigger is connected to the output of the second element OR C.

The disadvantage of such a device is its relative complexity.

The purpose of the invention is to simplify the device.

The goal is achieved by the fact that in a subtraction device containing two registers, two AND elements, an OR element and a delay element whose input is connected to the output of the first AND element, the output of the first register is connected to the first input of the second AND element, the output of which is connected to the input of the first the register introduced the EXCLUSIVE OR element, the output of which is connected to the input of the second register, the first input - with the direct output of the second register and the second input - with the output of the OR element and the first input of the first AND element, which is connected to the second and the third inputs respectively to the inverse output of the second register and to the device reset bus, the output of the first register is connected to the first input of the OR element, the output of the delay element is connected to the second inputs of the OR element and the second I.

The drawing shows a block diagram of a device for subtraction.

The proposed device contains two registers 1 and 2, the element 3 delay, two elements AND 4 and 5, the element OR 6, the element EXCLUSIVE OR 7 and the bus 8 reset.

The input of register 1 is connected to the output of element AND 5. The input of register 2 is connected to the output of the element EXCLUSIVE OR 7, the first input of which is connected to the direct register code 2, and the second input to the first input of element AND 4 and the output of the OR circuit 6.

The output of the delay element 3 is connected with the first element of the AND 5 element and the OR element b, which is connected to the output of the register 1 and BTOpc iy input element AND 5 by the second input.

The input of the delay element 3 is connected to the output of the AND 4 element, the second and third inputs of which are connected respectively to the inverse output of the register 2 and to the reset bus 8.

The device for the subtraction works as follows.

Register 1 contains the binary code of the deductible, and register 2 contains the decremented code. At the output of the element 3 delay acts zero signal. Binary codes of the subtracted and decremented are read from the outputs of registers 1 and 2 sequentially, beginning with the least bit. The inputs of the EXCLUSIVE OR 7 element receive signals of binary codes decremented and subtracted, respectively, from the output of register 2 and through the OR-6 element from the output of register 1. The EXCLUSIVE OR element 7 modifies modulo two binary codes of decreasing and subtracting and the result is written to register 2. In this time, the low bits of the subtracted are erased by AND 5, which is covered by the zero output signal of delay 3

This continues until the first combination of the subtracted single code and the zero code of the reduced one. In this case, the element 4 is triggered, at the output of which a single signal is generated. In the next cycle, a single signal output element And 4 begins to act on the output of the element 3 delay, which leads to the opening of the element And 5 and the formation of the output element OR b of a single signal.

After the first combination of 1-0 codes of the subtracted and decremented element, AND 4 is maintained in the open state by a single signal of the element OR b to the signal of the first unit of the decremented one, which, coming from the inverse output, register 2, puts the element 4 in the closed state. In the next clock cycle, zero the output signal of the element 4 begins to act at the output of the element 3, returning the device to its initial state.

Thus, after the first combination of 1–0 codes of the subtracted and reduced to the first unit of the reduced, including the processing time of this bit reduced, the output of the delay element 3 is a single signal that keeps the element and 5 in the open state and through the element OR b ° supports a single signal at the second input of an EXCLUSIVE OR 7 element, which places the EXCLUSIVE OR 7 element in the inversion mode of the binary code decremented. In this case, from the output of register 2 to its input, the inverted code of the decremented code is written, and from the output of register 1 to its input through the element 5, the binary code of the readable is rewritten without change.

Further calculations are repeated in the same way until register 1 is completely cleared. In register 2, the binary difference code is recorded.

If the decrement is less than the deductible, then the difference is formed in the additional code.

The computation time is one or several cycles, where the cycle takes n cycles (n is the number of bits of binary codes decremented and subtracted).

At the end of each cycle, the device returns to its original state with the help of a time signal of the polarity of the current 8 reset at the time of reading from the outputs of registers 1 and 2 of the last nth bits. The reset signal received through the bus 8, closes the element And 4, which by the beginning of the next cycle, the formation at the output of the element 3 delay of the zero signal.

Example 1. It is required to calculate the difference Z Y - X at Y X After two cycles of calculations, we get the result

HrO.010110111011010

YoO.fOOTOllllOOOOOll

.010000011010000

Wui 0.011101001111001

.000000000000000 Z X, 0.001100110101001

The bars mark the bits following the first one, starting with the lower bits, combination of codes 1, up to the first unit decreasing inclusively. This trait in the subtracted X marks the bits that are saved in the next computation cycle.

In decreasing V, this line is the designation for the operation of inverting the marked bits to be decremented.

The code decremented in each cycle is converted into a difference code by summation. modulo for all, except for those marked with a stroke, bits, subtracted and decremented, and in those marked with a stroke, the difference code is formed from the inverted code with decrement.

The point marks the sign bit, which is processed along with all bits.

Example 2. It is required to calculate the difference 2 Y -. X at Y C X In this case, the difference is formed in the additional code.

Ho.101001110010001

UoO.011110111011000

.000000000000000

Z - 1.110101001000111

in this example, to generate 5 binary difference codes required, with one cycle of calculations.

The technical advantages of the proposed subtracting device in comparison with the known is to reduce hardware costs.

The implementation of the proposed device for subtraction requires two registers, a delay element and four logic elements, which allows to simplify the device by one trigger, one delay element and one logical element.

Claims (3)

1. USSR author's certificate 435523, cl. 606 F 7/385, 1974. 2. USSR author's certificate for application number 2586372 / 18-24, cl. 606 F 7/385, 1978. 3. USSR author's certificate according to the application No. 2691127 / 18-24, cl. 606 F 7/385, 1978 (prototype).