SU847374A1 - Analogue storage - Google Patents

Description

The invention relates to an analog technique and can be used to memorize the range of a two-pole signal. An analog maximum-memory (AMC) is known that allows operation in a wide dynamic range. This AMC contains an amplifier, a key, a source follower, a capacitor, and a comparator 1. However, such a device allows one to memorize pulses of one polarity. The closest to the proposed technical entity is an analog storage device that additionally contains a comparator and an exclusive OR circuit, which allows you to remember the amplitude of pulses of any polarity 2. However, this AMU does not allow you to remember the amplitude of the two-polar signal. In addition, the presence of the bias voltage of the comparator leads to a decrease in the accuracy of the CAM. The circuit of the invention is to improve the accuracy of the device and expand its use by increasing the range of input signals. . The goal is achieved by the fact that in an analog storage device containing an amplifier whose input is connected to the device input and to the inverting inputs of the comparators, the non-inverting input of the first of which is connected to the zero potential bus, one of the outputs of the first comparator is connected via a delay element to the input of the inverter, the output of the amplifier is connected through a series-connected first switch, the first source follower and the second switch with a non-inverter, a Tirukadim terminal of the second comparator, a storage element , for example, capacitors, some of whose plates are connected to a zero potential, and other capacitor plates are connected respectively to the outputs of the generator of discharge pulses, the input of which is connected to the reset bus, the third and fourth keys, And elements, the second source follower, amplifier output connected via a series-connected third key, second source follower and fourth key with a non-inverting input of the second comparator, whose outputs are connected

respectively, with the first inputs of the elements AND, the second inputs of the elements AND, respectively, are connected to the input and output of the inverter, the outputs of the first comparator are connected to the control inputs of the second and fourth keys, the outputs of the elements AND are connected to the control inputs of the first and third keys.

The drawing shows a functional diagram of the proposed device.

The device contains an input 1 of the device, amplifier 2, keys B-B, coparators 7 and 8, source repeaters 9 and 10, elements 11 and 12, delay element 13, inverter 14, accumulator elements, for example, capacitors 15 and 16, driver 17 bit pulses, device outputs 18 and 19, and reset bus 20.

The device works as follows.

In the initial CONDITION, the capacitors 15 and 16. are discharged with the help of the imager 17. When a two-signal signal arrives at the device input, for example, a positive wave first goes, the comparator 7 is in the off state, while at its direct output it is zero, and inverse - one, then the key 6 is open, and the key 4 is closed. Comparator 8 is also turned off and at its direct output is zero, and at the inverse is another device. After a time determined by the delay of the element 13, a pulse from the comparator 7, inverted by the element 14, closes the switch 3 through the element 11 and the capacitor 15 begins to charge. Since the gain of amplifier 2 is greater than unity, the charging rate of capacitor 15 is higher than the rate of change of the input signal, so after some time the voltage at output 18 exceeds the value of the input voltage, which leads to switching of the comparator 8, and, therefore, and to open the switch 3. When the input signal again exceeds the voltage on terminal 18, the comparator 8 will trip again and the switch 3 will close. The capacitor 15 is charged again. This continues until the voltage at output 18 becomes equal to

18 X® SALKOMP.

where the bias voltage of the comparator 8;

Unva, - input impulse amplitude tS

pulse of positive polarity.

When the input signal decreases, the voltage at the output 18 does not change, since the key 3 is open and the charge leakage through the source follower 9 is minimal. By changing the polarity of the input signal, the comparator 7 tilts, resulting in

the key 6 is opened and the key 4 is closed. Since a negative polarity impulse arrives, the comparator 8 tilts and the key 5 closes through the element 12. 12. The capacitor 16 starts charging as described above until the maximum value of the negative wave signal is reached.

After charging the capacitor 16, the voltage at output 19 becomes

equal to the maximum value of the negative waveform

4fq - SM.K.OLLP1

where is U -..- ,. - the amplitude of the input pulse C

Sa negative surface.

Thus, at the output of the device between outputs 18 and 19, at the end of the output signal, there will be a voltage equal to

-OUT UBX® -,

(which can be removed with a differential amplifier), i.e. the voltage at the output of the device is equal to the maximum swing of the input signal, thereby expanding the range of input signals, and the comparator bias voltage is eliminated, which increases the accuracy of the device.

Claims (2)

1. Author's certificate of the USSR 639022, cl. G 11 C 27/00, 1979. 2. Authors certificate of the USSR 728162, class, G 11 C 27/00, 1978 (prototype).