SU843262A1 - Signal quality evaluating device - Google Patents

Description

The invention relates to a technique for transmitting discrete information and can be used in signal quality detectors (DXCs). It is known to a device for evaluating a signal quality comprising successively connected weight adder-amplifier, the first and second inputs of which are fed from the outputs of the first and second subchannels of the receiver, respectively, the first peak detector, the first drive, the first key, the first integrator, the first threshold unit and the first the OR element, the second input of which is connected to the output of the second threshold unit, the signal input of which is combined with the signal input of the first threshold unit, with the output of the weight adder-amplifier and with the input of the second peak detector, the output of which is connected through the second storage device connected in series, the second key and the second integrator is connected to the input of the alarm setup of the second threshold unit, where the output of the first OR element is connected to the amplifier input and to the input of the normalizer - the signal duration a third key and a switch connected in series are connected to the second inputs of the first and second drives and to the first input of the second OR element, the output of which is connected to the second inputs n The first and second keys, E are also serially connected analysis time counter, the third element OR, the adder and the third threshold unit, the output of which is connected to the second inputs of the third element OR, the switch and the third, the output of which is connected to the second input of the second element OR C AND However, the known device has a low estimation accuracy. The purpose of the invention is to improve the accuracy of the assessment.

The goal is achieved by the fact that the device for assessing the quality of the signal, containing serially connected weights, has the first and second inputs of signals from the outputs of the first and second subchannels of the receiver, the first detector, the first drive, the first drive, the first integrator, The first threshold unit and the first SHS element whose second input is connected to the code of the second threshold unit, whose sigal input is combined with the signal input of the first threshold unit, from the output m of the weight adder-amplifier and with the input of the second pin detector, the output of which is connected through the second storage device, the second switch and the second, in series; the integrator is connected to the input of the threshold setting of the second threshold unit, and the output of the first element OR is connected to the input of the amplifier the duration of the signal, the output of which is connected through the third key and the switch connected in series with the second inputs of the first and second drives and with the first input of the second element. Connected to the second: the primary inputs of the first and second keys Ja are also series-connected analysis counter, the third element of the ShZh, the adder and the third threshold unit, the output of which is connected to the second input of the third SHS element, the switch and the third key, the output of which is connected to the second input of the second element OR, the serially connected counter of the duration of the code combination and the unit of the combined signals and the serially connected first element AND, summing counter, subtractor counter, second element AND The prohibition element, while the output of the first element OR is connected to the first input of the first element AND, whose second input, combined with the input of the code combination duration counter and the second input of the prohibition element, receives the clock frequency signal of the receiver, the output of the prohibition element is connected to the second input of the subtracting counter and - with the second input of the adder, and the input of the analysis time counter is connected to the first output of the counter

A code combination, the second output of which is connected to the V1SODOM of the summing counter, the third input of which is connected to the output of the signal combining unit, to the second input of which a receiver error signal is applied.

The drawing shows a structural electrical circuit of the proposed device.

A device for evaluating signal quality contains a weight combiner 1, first and second peak detectors 2 and 3, first and second drives 4 and 5, first, second and third keys 6.7 and 8, first and second integrators 9 and 10, first , second and third threshold blocks II, 12 and 13, respectively, amplifier 14, switch I5, adder 16, first, second and third elements OR 17.18 and 19, respectively, counter 20 analysis time, normalizer 21 signal duration, prohibition element 22, the first and second elements of And 23 and 24, respectively, the block-25 combining signals, with counter 26 of the duration of a code combination, a summing counter 27, a receiver 28, a subtractive counter 29

The device works as follows.

The received signal from the output of receiver 28 through the weight adder-amplifier 1, detectors 2 and 3, drives 4 and 5, keys 6 and 7, integrators 9 and 10 are fed to threshold blocks P and 12. Threshold blocks II are supplied with a threshold voltage. The erase signals are separated by intersecting the original signal with the reference voltage. From the outputs of the threshold blocks 11 and 12, the erase signals are combined in the first element OR 17 and are fed to the input of the first element AND 23, and the second frequency is supplied to the second input of the first element And 23. The erase signal is released when the clock and erase signals match. With such a connection, not more than one signal is allocated to each single element. Erasing from the output of the first element AND 23, erasing signals are fed to the input of the totalizer of the counter 27, In the summing counter 27, the number of erasures per period is accumulated

equal to the duration of the code combination,

Consider the case when the decoder does not detect an error in the duration of a code combination. The erasers present are considered false. The read signal from the output of the counter 26 information is rewritten into subtractions of the counter 29. At the end of the duration of the code combination, the signal from the other output of the counter 26, through block 25, the summing counter 27 returns to its original state. At the input of the subtractor counter 29, the prohibition element 22 begins to receive the clock frequency from the output of the receiver 28. The clock frequency is used to subtract from the recorded result until all the triggers of the subtractive counter are set to the initial state. In this case, a signal is prohibited from the second element AND 24 of the prohibition against the element 22 of the ban. With the arrival of the signal, Zatsret stops the passage of the clock frequency to the input of the subtracting counter 29. The number of frequency cycles is exactly equal to the number of false erasures recorded in the subtractive counter 29. From the output of the block 22, the clock frequency corresponding to the number of false -s. erase on the duration of the code combination, is fed to the input of the adder 16, where there is an accumulation of the number of false erasures during the analysis time determined by the counter 20 of the analysis time. If the number of false erasures is greater than the predetermined number, then the threshold unit 13 is triggered and the threshold is adjusted.

If at least one error is detected by the decoder for the duration of the code combination, then all erasures are considered correct. The error signal from the output of the receiver 28 through block 25 completely accumulates information from the summing counter 27 is erased, the triggers are reset to their original state. Then the error signal is followed by a read signal from the counter output.

26. At the end of the duration of the code combination, the signal from the other output of the counter 26, through block 25, enters the summing counter

27, duplicate the error signal from the output of 1 receiver 28 ..

Claims (1)

Invention Formula A device for evaluating the quality of a sinal, containing a series-connected weight adder-amplifier, the first and second inputs of which receive signals from the output of the first and second subchannels of the receiver, the first peak detector, the first drive, the first key, the first integrator, the first horn block, and the first element 11LI, the second input of which is connected to the output of the second threshold unit, the signal input of which is combined with the signal input of the first threshold unit, with a high voltage, m weight adder and with an input ohm second peak detector, the output of which is connected through the second storage device connected in series, the second key and the second integrator are connected to the input of setting the threshold of the second threshold unit, the output of the first element OR is connected to the input of the amplifier and to the input of the normalizer of the signal duration, the output of which is connected through the third key and the switch is connected to the second inputs of the first and second drives and to the first input of the second ILS element, the output of which is connected to the second inputs of the first and second key, as well as serially connected analysis time meter, the third element OR, the adder and the third threshold block, the output of which is connected to the second inputs of the third OR element, the switch and the third key, the output of which is connected to the second, input of the second OR element, different that, in order to improve the estimation accuracy, a serially connected counter of the duration of a code combination and a signal combining unit and a serially connected first element I, summing a counter, subtracting a counter, are introduced k, the second element And the element of the prohibition, while the output of the first element OR is connected to the first input of the first element AND, the second input of which, combined with the input of the code combination duration counter and the second input of the prohibition element, receives the clock frequency signal of the receiver, the output of the prohibition element connected to the second input and the second input of the adder, and. The input of the analysis time counter is connected to the first output of the code combination duration counter, the second output of which is connected to the second input of the summing counter, the third input of which is connected to the output of the combining unit signals whose second input is a receiver error signal, Sources of information taken into account in the examination J. CCYTT, Special Study GrouR A, Signal Quality Detector with Self adjusting Thresholds ,, Contribution,, No. 71 (prototype).