SU1319293A1 - Device for predicting state of digital communication channel - Google Patents

Abstract

The invention relates to telecommunications and improves the prediction accuracy. The device contains error counter 1, time interval former 2, prediction block 5x2 3, forecast evaluation block 4, decoders 5-7, keys 8-12, adders 13 and 14, counters 15-17, divider 18, RS trigger 19, blocks 20 and 21 of memory, el-t 22 delays, display units 23. The predicted number of errors is compared with the actual in block 4. If the number of errors does not match by the amount exceeding the permissible prediction error, block 4 generates a signal specifying the algorithm of operation of block 3. In the decoder 5, the expected number of errors is compared with the set the threshold value, and at the output a signal of evaluation of the quality of the communication channel is formed, which enters the block 23. 1 Il. with with K5 WITH with

Description

The invention relates to telecommunications and can be used to control the quality of a discrete communication channel.

The purpose of the invention is to increase the reliability of forecasting.

The drawing shows a structural electrical circuit diagram of a device for predicting the state of a discrete communication channel.

The device has 1 error counter,

the input of the second adder 14. The signals of the imaging unit 2 time interval through the open first key 8 are fed to the inputs of the counter 16, the first block 20 and they and read the signals “Error, P |, P2, pz, ..., P to the sum input the second adder 14, on subtracting, whose input signals are received “Error nl, nz, pz, ..., nk from the output of the counter 1 errors. From the output of the second adder 14 differential signals ni-P2,

shaper 2 time intervals, block 3U pz-n 2, pz-p 3, at time points

prediction, block 4 forecast estimates, ti, t2, 1h, ..., U arrive at the summing .first-5, second 6 and third 7 decoders, the first - fifth keys 8-12, the first

13 and second 14 adders, first 15, input to the third counter 17, where the summation of the difference signals is performed.

From the third input of the device, the signal 16 and the third 17 counters, a divider corresponding to the time of 18, the RS flip-flop 19, the first 20 and the second IN, for which 21 memory blocks, a delay element 22 and a display 23 are needed.

The device works as follows. The signals “Error P |, P2, pz, ..., detected and counted by the counter 1 error - 20”, determined in the previous cycle, side by side for the time intervals ti, iz, is, ---, are assigned to the input the first adder 13. Bloomed by the shaper 2 time interval, is fed to the input of block 3, predicts the number of errors, comes through the input delay element 22 of the second memory block 21, from which output the number of errors n for a moment in time

In addition, the control signal opens the second key 9. The value of the N measurement cycle from the output of the second decoder 6 through the replay, which determines the amount of spin, the control signal opens the second key 9. The value of the N measurement cycle from the output of the second decoder 6 through the prediction interval time key 9 enters the control

the input of the divider 18 and sets its division ratio to N. Fifth key 12 is open and the values of the third counter 17 are received at the information input of the divider 18, the output of which is (P1-rii) + (P2-P2) + (Pz-Pz) + + () whether

The first adder 13 produces a summin. The predicted number of errors is compared with the actual in block 4 of the forecast estimate. If the number of errors does not coincide by an amount exceeding the permissible forecast error, the forecast evaluation unit 4 generates a signal specifying the algorithm, Qth the private rhythm signal of the prediction unit 3, In the first decoder 5, the expected number of errors generated by the prediction unit 3 is compared with the set nopoi OBbiM value. Depending on the achieved threshold at the output of the first one, the values of PN and Dp. At the output of the decoder 5, a signal of the corresponding adder 13 is formed;

evaluation of the quality of the communication channel is equal to the number of errors in the interval

which enters the block 23 of the projection map U. The third decoder 7 on the osnoni. In the absence of a signal, the "Avarie of the reached threshold generates the third body signals for the display unit 23, executed as the output of the first decoder 5

key 10 is open and signals "Error ni, 02, 40" When a signal appears, "Avariya at the exit, ... ... from the error counter 1, the first decoder 5 hopes the third key 10 locks and the third counter 17 is reset. Upon the restoration of communication, the process of analyzing the VII of the communication channel by technical standards is not repeated. The delay time of the output element 22 of the first decoder 5 appears selected based on the time of a valid вари avariy signal, which closes the third key 10 and reads the value of the first counter 15 to the input of the display unit 23, which displays the time interval tn, at which Avariu occurred, t. e. In-50 processing to failure. After the communication channel is restored, the signal "The channel is restored via the second input of the device is fed to the R input of the RS flip-flop 19, at the S input of which the signal" Norm is present. At the exit

RS flip-flop 19 is a logical level, b, 55, the first input of the error counter, the second opens the first key 8 and is connected to the first input of the device, the second

with the fourth key 11 you input is connected to the driver output

stroke of error counter 1 to the subtracted time interval, and the output through the block

the inputs of the first 20 and second 21 memory blocks, in which they are stored for the entire operation of the device. In case of incompatibility, divider 18.

Claims (1)

Invention Formula A device for predicting the state of a discrete communication channel, comprising a prediction evaluation unit, a time interval generator and serially connected error counter, a prediction block, a first decoder and a response unit of the second adder 14. Time interval 2 signals are transmitted through the open first key 8 to the counter inputs 16, of the first block 20 Iam tees and read the signals “Error, P |, P2, pz, ..., Py to the summing input of the second adder 14, to subtract, whose input receives the signals“ Error nl, nz, p c , ..., nk with out a counter 1 errors. From the output of the second adder 14 differential signals ni-P2, pzp 2 pzp at time points  the corresponding time IN, for which it is necessary to define, defined in the previous cycle, enters the input of the first adder 13. The number of errors is passed through the delay element 22 to the input of the second memory block 21, the output of which errors n for a point in time In addition, the control signal opens the second key 9. The value of the N measurement cycle from the output of the second decoder 6 through the second key 9 is fed to the control swarm key 9 goes to the control the input of the divider 18 and sets its division ratio to N. Fifth key 12 is open and the values of the third counter 17 are received at the information input of the divider 18, the output of which contains the signal of the partial values PN and Dp. At the output of the first adder 13 there is a value (P1-rii) + (P2-P2) + (pz-Pz) + + () whether The first adder 13 produces the sum of the signal private value of the values PN and Dp. At the output of the first adder 13 there is a value piranya the third key 10 and resetting the third counter 17 to the initial state. Upon the restoration of communication, the analysis process is repeated. The delay time of the element 22 is chosen based on the time of a valid expression; the first input of the error counter is the first input of the device, the second bots divider 18. Invention Formula A device for predicting the state of a discrete communication channel, comprising a prediction estimation unit, a time interval generator and serially connected error counter, a prediction unit, a first decoder and a prediction evaluation unit, is connected to another input of the prediction unit, the output of which is connected to another input of the forecast evaluation unit, characterized in that, in order to increase the reliability of the prediction, a first counter, serially connected RS flip-flop, first key, second counter, second decryptor, second key, divider, first adder and third decoder, serially connected third key, fourth key, first memory block, second adder, third counter and fifth key, serially connected delay element and second memory block, the output of which connected to another input of the first adder, and another input connected to the output of the third key, whose information input is connected to the output of the error counter, and the controlling the input is connected to the output of the first decoder, to other inputs of the second and third counters, to the S input of the trigger and to the control input of the first counter, the output of which is connected to the second input of the display unit, and the information input is connected to the output of the time interval former and to another input the first key, the output of which is connected to another input of the first memory block, the / input of the trigger is the second input of the device, and the output is connected to another input of the fourth key, the other output of which is connected to another input of the second th adder, the output of the third decoder is connected to the third input of the display unit, the input of delay element connected with the control inputs of the second and third keys, and is a third input device.