SU840956A1 - Function generator - Google Patents

Description

(54) FUNCTIONAL BREAKER

The invention relates to analog digital and computer technology. A well-known functional generator is known that contains a pulse generator, a counter, a decoder, a sawtooth generator, a comparator, a variable gain block and an output amplifier, a filter. The disadvantages of this converter are reduced accuracy in generating one variable for the second variable and the complexity of the circuit. A functional 1 converter is known, containing a block of digital-analog multiplication, outputs: one amplifier filter, a pulse generator connected by output E to a clock input. pulses of a linear porosity unit, an analog-to-digital diffraction unit, the input of which is the first input of the functional transducer, and the high-order outputs are connected to the inputs of the address decoder connected to the outputs of the address of the memory and the memory, the second inputs of the memory module are the second input of the function generator, and the outputs of the memory block are connected to the outputs of the output filter amplifier, the output of the block and the analogue conversion connected by digital clock E to the bit outputs of the analog-digital block The first transformation is connected to the first input of the adder, the second input of which is connected to the input of the avalo-digital power generation unit, and the output is connected to the input controlling the duty cycle of the linear duty cycle unit connected; output to the control input of the readout of the decoder 2.: the accuracy of the formation of the u) izizvedenin functions of one variable on the second variable, due to, in most cases; analog representation, the ordinate of the nodes of the approximation and the operation of multiplying by the second variable by

voltage changes at the second inputs of the memory block, as well as high hardware costs.

The closest technical solution to U) is a functional converter containing a memory block, first and second blocks of cyanalog multiplication, analog inputs, which are connected and altered by the first input of the converter, an output filter amplifier, whose output is the output of the converter, pulse generator connected by an output to an input of clock pulses of a linear duty cycle unit, an address decoder whose outputs are connected to the address inputs of a memory unit, an analog-to-digital conversion unit and the input of which is the second input of the functional converter, the outputs of the higher bits are connected to the inputs of the Aires decoder, and the outputs of the lower bits are connected to the control inputs of the linear duty cycle unit, two groups of elements And, inverter, digital inputs of the first and second blocks of digital-analog multiplication connected to the outputs of the first and second groups of elements And, respectively, the output of the linear duty cycle unit is connected to the first inputs of the elements of the first group and to the input of the inverter, the output of which is connected to the first Bx The odes of the elements of the second group, the second inputs of the elements of both groups are connected to the outputs of the memory block, the outputs of the first and second blocks, the digital-to-analog multiplication are connected, to the input of the filter amplifier 3.

The disadvantages of the proposed converter are the reduced performance in connection with the time-pulse control of supplying the nodal ordinate codes of a given function to the digital inputs of the digital-to-analogue multiplication blocks.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that the functional converter containing the memory block, the first and second digital-analog multiplication blocks, the analog inputs of which are connected and are the first input of the converter, the output filter amplifier whose output is the output of the converter, pulse generator, connected the output to the input of the clock pulses of the linear duty cycle unit, the address decoder, the outputs of which are connected to the address

the inputs of the memory unit, the analog-digital conversion unit, whose input is the second input of the function converter, and the higher-order outputs are connected to the inputs of the address decoder, and the low-level outputs to the control inputs of the linear duty cycle unit, the inverter connected by the input to the output of the linear unit duty cycle, additionally contains the first and second keys, the information inputs of which are connected respectively to the outputs of the first and second digital-analog blocks. multiplying, the control inputs are respectively with the outputs of the linear duty cycle unit and the inverter, and the outputs are with the amplifier input filter, the digital inputs of the first and second digital-analog multiplication units are connected to the outputs of the memory unit.

The drawing shows the block diagram of the Converter.

The functional converter contains the first 1 and second 2 blocks of digital-analog multiplication, the first 3 and second 4 keys, the output amplifier filter 5, the inverter 6, the pulse generator 7, the analog-digital compression block 8, the linear-duty cycle 9, the address decoder 10, the And memory block ti.

Functional Converter works as follows.

Claims (3)

The argument X of the reproduced function f (x) in analog form comes from the second input of the converter to the input of block 8 of the analog-digital converter, from the output of which in digital form the lower bits goes to the control inputs of the duty cycle of block 9. Block 9 of the linear duty cycle converts the argument X to square-wave pulses, the duty ratio of which E varies from X according to a triangular law, and the frequency of the pulse is determined by the generator 7 of pulses. From the output of block 8 of the analog-to-digital conversion, the high-order bits of the transformed argument X through the decoder. 1O, the addresses control the operation of memory block 11 in such a way that alternately even Nj appear alternately on its first and second output registers; codes of ordinates of nodes approximation of the function f (x). In this case, the change of codes occurs at the moments when the arguments of the X values of the codes are reached — when the values of X X, i 1, 2, ... and MjJ control the transmission coefficients of the first 1 and second 2 blocks of digital-analog multiplication, respectively, multiplying the voltage of the first input of the converter by these codes. These products from the outputs of the first 1 and second 2 digital-to-analog multiplication units are received at the information inputs of the first 3 and second 4 keys, respectively, the control inputs of which are supplied by square pulses from the output of block 9 of the linear duty cycle and from the output of inverter 6. Since the duty cycle is square pulses at the output of block 9 are varied according to a triangular law 9, and at the output of inverter 6 according to a triangular law 0 cn. 1 -® at the output of the amplifier filter 5 forms voltage ()) Н, 1, where V, (x) and Vi (x) are the triangular functions of the argument X, defined by the laws of variation of the ratio of 8 and 1-0, t. e. the function converter performs an operation of multiplying the input signal i by the function C (x). The change of codes at the digital inputs of the first 1 and second 2 digital-to-analog multiplication units occurs once during the two approximation sections, while in the known invention this change occurs many times more often with the frequency of square impulses of the linear-duty cycle unit 9. As a result, the first 1 and second 2 blocks of digital-analog multiplication, compared with the known invention, are simpler and have a smaller bandwidth, and with the same bandwidth can dramatically increase the speed of the converter as a whole. In the proposed converter, it is necessary to implement only two keys - the first 3 and second 4, which does not cause technical difficulties, while in the known invention the same speed requirements are imposed on two blocks of digital-analogue reconstructed Claims. The functional converter containing the memory block, the first and second blocks of qi (analog multiplication, the analog inputs of which are connected are the first input of the converter, the output amplifier filter, the output of which is the output of the converter, a pulse generator connected by the output to the input of the clock pulses of the linear block the duty cycle, the address de-interpreter, the outputs of which are connected to the address inputs of the memory unit, the analog-to-digital converter unit, the input of which is the second input — the functional pre- The upper bits are connected to the address inputs of the address, and the low bits are connected to the inputs of the control of the duty cycle of the linear duty cycle, the inverter connected to the output of the linear duty cycle, characterized by the fact that in order to improve speed, it also contains the first and second keys, the information inputs of which are connected to the outputs of the first and second blocks of digital-analogue multiplication, the control inputs, respectively, to the outputs of the linear duty cycle unit and the inverter, and the outputs - with the input of the filter amplifier, the digital inputs of the first and. The second digital-to-analog multiplication units are connected to the outputs of the memory unit. Sources of information taken into account during the examination 1 1. US Patent No. 3689754,, cl. 235-197, publ. 1972., 2. Korn G. and Korn T. Electronic Analog and Analog-Cis Computational Machines. M., Mir, 1968, Part 2, p. 218-219. 3. USSR author's certificate for application No. 2542926 / 18-24, cl. G About Q 7/26, 1977. I Iff b-5 lisuK yff i s t