SU834572A1 - Parallel analog-digital spectrum analyzer - Google Patents

Description

• The invention relates to measuring technique and can be used in the analysis of spectra of low and infra-low frequency signals.

Known analog-to-digital analyzers containing input filters, a detector, a switch, a control unit and a GM indicator, however, their measurement accuracy is insufficient. ₁₀

The purpose of the invention is improving the accuracy of measurements.

This goal is achieved by the fact that · in a parallel analog-to-digital spectrum analyzer containing Pospelov — _{15 well-} connected bandpass filters, a detector, a low-pass filter and a switch., As well as a control unit and an indication unit, an additional channel number counter, a start unit, a buffer memorizing device, a conjunctor, a distributor, and an analog-to-digital converter connected between the output of the switch and the input of the start-up unit, one of which is connected to the control input of the commutator through a channel number counter Ator, the other output is connected to the second input of the analog-digital converter, and a third output coupled to an input conjunctor, the output channel number of the counter, the second output of the analog-digital converter and an output. the conjunctor is connected to the inputs of the buffer storage device, the output of which through the distributor is connected to the display unit, and the outputs of the control unit are connected to the control inputs of the distributor, display unit, buffer storage device, start tag and the second input of the conjunctor.

The drawing shows a functional diagram of the analyzer.

It contains a band-pass filter I, detector 2, low-pass filter 3, switch 4, analog-to-digital converter 5, start-up block 6, channel number counter 7, buffer memory 8, coupler 9, control unit 3 83 ^z with output 11 of external control, a distributor 12 with an output 13 to an external reader (not shown) and a display unit 14.

The analyzer works as follows.

After the analyzer is turned on, the control unit 10 generates a signal arriving at the start-up unit 6, according to this signal, the start-up unit b makes an initial start-up of the analog-to-digital converter 5. At the same time, the start-up unit 6 generates a counting signal arriving at the channel number counter 7. Based on this signal, the channel number counter 7 generates the code of the first channel, which is fed to the switch 4 and to the buffer memory 8. At the same time, the switch 4 passes the signal of the first · selective channel to the analog-to-digital converter 5. At the end of the conversion of the analog value of the measured signal to digital analog-to-digital Converter 5 generates a signal The end of the conversion received by the block 6 start. Moreover, the conversion time is proportional to the signal level, and at a zero signal level, the analog-digital converter 5 generates a signal. The end of the conversion immediately after the start signal.

The digital code is received from an analog-digital converter 5 for recording in a buffer memory 8, which also continues to receive the code of the first channel.

Thus, the number of the selective channel is linked to the signal level in this channel.

The control unit 1O generates alternately recording and reading information signals. When the connection signal 9 matches the recording signal and the signal from the start block 6 generated by the signal End of conversion, the digital code is written to the buffer memory 8 in the memory cells determined by the code of the first channel. At the end of conversion signal, the start-up block is broken in the start-up block, and from that moment on, the start-up block 6 generates start-up signals autonomously by the end-of-conversion signal with a small time shift necessary to write the digital code to the buffer memory 8. Simultaneously to the counter 7 channel numbers counting signals are received

1572 4 channels that convert the counter to the state of the L-th channel.

After polling the last election channel, the counter 7 of the channel number goes into the state of the first channel, and the polling cycle of the selective channels is repeated.

The information is read from the buffer random access memory 8 10 by the signal. The information is read and the code of the memory cell number generated in the control unit 10. The code 'memory cell number corresponds to the channel number code.

There are two types of information output: the first to the display unit 14 and the second to an external reader. To provide information to an external reader, a control signal from an external reader is supplied to the control unit 10. The control unit 10 generates control signals for the buffer memory 8, the indicating unit 14 and the distributor 12, which transmits information to both the indicating unit 14 and the pauses between the signals arriving at the indicating unit 14 and to the input of an external reading device.

Thus, the frequency spectrum is simultaneously displayed on the display unit 14 and the spectrum is estimated on a time scale that is close to real.

Claims (1)

(54) PARALLEL ANALOG-DIFFERENTA SPECTRUM ANALYZER with the output 11 of the external control, the distributor 12 with the output 13 to the external reader (not Pozkazano) and the display unit 14. The analyzer works as follows. After turning on the analyzer, the control unit U forms a signal arriving at the start block 6, and according to this signal the start block 6 makes an initial start of the analog-digital converter 5. At the same time, the start block 6 generates a counting signal arriving at the channel number counter 7. According to this signal, the channel number counter 7 generates the code of the first channel that goes to switch 4 and buffer storage device 8. At the same time, switch 4 passes the signal of the first selective channel to analog-to-digital converter 5. After the conversion of the analog value of the measured signal to digital Analog-to-digital converter 5 generates a signal of the Conversion End arriving at the start block 6. At the same time, the Ba1sh time transform is proportional to the signal level, and at a zero signal level, the analog-to-digital converter 5 generates a signal to the Conversion end immediately after the trigger signal. The digital code comes from an analog-to-digital converter 5 for writing to the buffer memory 8, which also continues to receive the code of the first channel. In this way, the number of the selective channel is linked to the signal level in that channel. The control block generates the write and read information signals alternately. When the recording signal and the signal coming from the start block 6, generated by the End Conversion signal, match in the conjunctor 9, the digital code is written to the buffer memory 8 in the memory cells determined by the first channel code. The End of Conversion signal in the start-up block breaks the initial start-up formation circuit, and from that moment on, the start-up unit 6 generates start-up signals autonomously via the End-of-conversion signal with a small time offset needed to write the digital code to the buffer memory 8. At the same time, the counter 7, the channel numbers receive counting signals that bring the counter to the t-th channel state. After the last polling channel has been polled, the channel number counter 7 will move to the first channel state, and the polling channel polling cycle will be repeated. The reading of information from the buffer random access memory 8 takes place on a signal. Reading the information and the code of the memory cell number generated in the control unit 10. Code . cell number corresponds to the channel number code. There are two types of information output: the first is on the display unit 14 and the second is on the external reader. In order to provide information to an external reader, control unit 10 is supplied with a control signal from an external reader. The control unit 10 generates the control signals of the buffer storage device 8, the display unit 14 and the valve 12, which reads, sends information both to the reading unit 14 and to the pauses between the signals to the display unit 14 and to the input of the external reader. Thus, a simultaneous display of the frequency spectrum on the display unit 14 occurs and the spectrum is estimated on a time scale close to real. Claims of the invention A parallel analog-digital spectrum analyzer comprising a series-connected band-pass filter, a detector, a low-pass filter and a switch, as well as a control unit and a display unit, characterized in that, in order to improve measurement accuracy, a channel number counter is added to it, start-up unit, buffer memory, conjunctor, distributor and analog-to-digital converter connected between the switch output and the start-up block input, one output of which is through a number counter the channel is connected to the control input of the switch, another output is connected to the second input of the analog-digital converter, and the third output is connected to the input of the conjunctor, at. In this case, the output of the channel number counter, the second output of the analog-digital converter and the output of the conjunctor are connected to the inputs of the buffer memory), the output of which is connected to the display unit through the distributor, and the outputs of the control unit are connected to the control inputs of the distributor, block of indcadin, buffer memory dego device. 72 block start and the second input to konctor. Sources of information taken into account during the experiment 1. USSR Copyright Certificate № 468181, cl. b OtP 23/16, 1975. Vi t 10th gz J2 -