SU828362A1 - Device for control of multiphase static converter - Google Patents

Description

one

The invention relates to electrical engineering and can be used to control multiphase static converters (SPs).

A device for controlling a multi-phase dual-inverter SP with an output transformer is known, which uses a periodic synchronization signal, with respect to which the inverter control signals are shifted by the same angle, depending on the position of the synchronization points of intersection with an adjustable DC control voltage, and containing a pulse generator and a phase shifter 1. However, in such devices, the control range of the angle depends on the phase t and does not exceed O- / on.

A single-channel device for controlling a multi-phase SP containing two phaeo-splitters (FS), a phase-shifting unit (FSB) and a pulse generator 2 is known. The disadvantage of such a device is a limited control range that does not exceed O-2 l.

The purpose of the invention is to expand the phase control range (0 -: -) regardless of phase. transform.

The goal is achieved by the fact that the device for controlling multi-phase

The joint venture, which contains two FR, FSB and a pulse generator (GI), is equipped with two frequency dividers, the inputs of which are connected to the output of the impulse generator, AND and OR-NOT elements and two functional blocks, each of which has an input logic element NO connected to the input of the counting trigger, the outputs of which are through another element

NO and; element I is connected to a two-input element OR, which is connected to the input of the output frequency divider, the inverting input of the input element NO is connected to the output of the GI, which inverts

the input of another element is NO and another input of element I is with the output of the first frequency divider, the output of the output frequency divider is connected to the FR input, and the non-inverting input of the input element is NOT connected to the output of the FSB via the AND element of one and the YLI-NO element of another functional unit , and the output of the second frequency divider is connected to the input of the FSB and to the second inputs of the AND and ORINE elements.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - time diagrams; in fig. 3 — sawtooth period for explanation

device operation

The device contains FR 1, FR 2, FSB 3, functional blocks 4, 5, GI 6, the first frequency divider 7 with the division factor a and the second frequency divider 8 with the division factor 02, the elements AND 9, OR-NOT 10.

Functional block 4 (5) has an input element 11 (12) NO, connected to the input of the counting trigger 13 (14), the outputs of which through another element NO 15 (16) and element 17 (18) are connected to the two-input element OR 19 (20 ), in turn, connected to the input of the output divider 21 (22) with a division factor of az.

FR 1 (FR 2) is made according to a ring circuit, FSB 3 - with a sawtooth voltage generator 23 (STI) and comparison circuit 24. To the second input of the circuit 24 is connected a source of control voltage {YY in the form of a comparison circuit (not shown), which forms the error signal f / y between the output voltage SP and its nominal value.

The functional unit 4 (5) inverting input element 11 (12) is connected to the output of the GI 6, the inverting input element 15 (16) and the other input element 17 (18) connected to the output of the divider 7, and the output of the output divider 21 (22) - to the entrance of the FR 1 (FR 2).

In block 3: the output is connected to elements 9 and 10, and the input to the output of the divider 8, to which the second inputs of elements 9 and 10 are connected. The output of element 9 is connected to the non-inverting input of element 11, the output of element 10 is connected to the non-inverting input of element 12.

The device works as follows.

The GI generates a sequence of square-wave pulses with a frequency fo and a duty cycle (Fig. 2, C / B), which is converted in blocks 7 and 8 into pulse sequences with frequencies / o / ai (Fig. 2, Uj) and / 0/02 ( Fig. 2, C / c), respectively. The pulses with the following frequency / o / a2 are used to start the FPG 23. The sawtooth voltage from the FPG output (Fig. 2, C / 2h) does not reach the circuit 24, where it is compared with the control voltage P / V. As a result, a pulse is formed at the output of block 3, the duration of which varies from 0 to az / fo depending on the value of C / y (Fig. 2, U2i). A pulse from the output of block 3 is fed to elements 9 and 10. A pulse sequence with a frequency of / 0/02 is fed to the second inputs of these elements.

The duration of the pulses at the output of elements 9 and 10 depends on the magnitude of C / y, i.e. from the position of point A on the working path of the sawtooth voltage (Fig. 2, C / 2h). Three situations are possible.

I. Point A is above the C / O level () (Fig. 3). At the output of element 9, a pulse is formed with a duration of

1 02/2 / 0-7-0 (Fig. 2, Us). At the output of element 10, there is no pulse.

P. Point A lies below the C / O level (). Element 9 impulse output

missing. At the output of element 10, a pulse is generated with a duration of 2 0n-a2 / 2 / o (Fig. 2, C / o).

Iii. Point A lies in the middle of the working stroke. Impulses are absent on the outputs of elements 9 and 10.

The pulses from the outputs of elements 9 and 10 are fed to the inputs of blocks 4 and 5, respectively, in which the first and second pulsed complements are formed with a frequency of / o / aioa and a phase shift between them depending on C / y, also ai, a, a . Consider situation I. In situation I (), the first pulse sequence is formed in block 4. With element 11, interval ti is filled with a packet of inverted pulses with frequency / o (Fig. 2, C / and). The trigger 13 is switched on the leading fronts.

packet pulses (Fig. 2, k). The signals from the outputs of the trigger 13 and the divider 7 through elements 15, 17, 19 to the input of the divider 21 receives a sequence of pulses with frequency / o in the interval ti

and the frequency / o / ai outside the specified interval (Fig. 2, C / ig). From the output of the divider 21, pulses with frequencies (1 / o / a and a / 2 / o / ai az (Fig. 2, C / 2i) are fed to the input of FR 1, which is triggered on the leading fronts

these pulses.

The second pulse sequence in the same situation is formed in block 5. Since the output of element 10 and, accordingly, the output of element 12,

is absent, trigger 14 keeps element 18 open and element 16 is closed. As a result, a sequence of pulses with frequency / o / s passes through divider 22. After divider 22, pulses with frequency / 2 / fl / ai063 arrive at the FR 2 input. Phase shift over time ti between the first and second pulse sequences can vary from 0 to Cl.

In situation II () in block 4, a second sequence of pulses is formed with a frequency of / 2 / o / aia3, since at the output of element 9 and, accordingly, at the output of element 11, there are no pulses, trigger 13 opens element 17, closes

element 15, and pulses with frequency / o / oi are passed to the input of divider 21, where by dividing by az they are converted into a sequence with frequency / 2 / o / aia3.

The first sequence of pulses in

the same situation is formed in block 5. The interval tz formed at the output of element 10 is filled with inverted pulses with a frequency / o (Fig. 2, Uiz). The trigger 14 is switched on the front

the fronts of these pulses (Fig. 2, U). By

signals from the trigger outputs 14 and divider 7 using elements 16, 18, 20 to the input of divider 22 Receives a pulse sequence with a frequency fo in the interval tz and a frequency fo / cci outside this interval (Fig. 2, C / 2o) In the divider 22 it is converted into a sequence with frequency (1 / o / a and az and frequency / 2 fo / aia3 (Fig. 2)), which is fed to the input of FR 2.

The phase shift in time 4 between the first and second pulse sequences can vary from Kn to 0.

In situation III (), the device forms two sequences of pulses with a frequency fz folai az without a phase shift between them.

Thus, this device produces at the outputs of blocks 21, 22 two pulse sequences with equal frequencies, but different phase transitions between them. Any change in the phase shift between sequences of pulses leads to a change in the angle between the inverting voltages and, as a result, to a change in the output voltage SP.

Thus, for any change in the supply voltage or other external destabilizing factor leading to an increase or decrease in the output voltage of the SP relative to the nominal value, the device maintains the output voltage value at the level of the dimming.

Claims (2)

1. The patent of Germany No. 2231936, cl. H 02 P 13/18, 1970. 2.Patent of Great Britain No. 1371703, CL. H02M 1/08, 1971. t- -t f t