SU826329A1 - Device for interfacing on-line storage with multiprocessor computer control unit - Google Patents

Description

(54) DEVICE FOR STRETCHING OPERATIONAL

MEMORY WITH MEMORY MANAGEMENT DEVICE

MULTI-PROCESSOR COMPUTING MACHINES to service requests in the operational memory of several processors and input-output channels of the multiprocessor computer at the same time, providing independent and parallel service of requests for writing and reading information in or from the main memory, providing the combined service of several requests as read, so on the record. The goal is achieved by the fact that in the device containing the input register of the read information the first output of which is connected to the information input of the read information correction block, whose address input is connected to the first output of the decoder, and the output to the input of the output register of the read information, the parity checker the read information, the output of which is connected to the control input of the Hamming control code generator of the read information, the output of which is connected to the first input comparison circuits, a control unit, a parity check code generator, and an output register of recorded information, the output of which is the output of the device’s recorded information, an information switch, an address switch, a read information selector, an incomplete word selector, an address storage block, an accompanying storage unit are entered information, the input register of the recorded information, the driver of the control code for the parity of the corrected information and the driver of the control Hamming code of the recorded information, and the control input of the Hamming control code generator of the recorded information is connected to the output of the parity check code generator, the output is connected to the output control register of the recorded information, and the information input is connected to the input of the parity check code generator of the recorded information, information the input of the output register of the recorded information and the output of the input register of the recorded information, the input of which is connected to the output of the selector an incomplete word whose full word input is connected to the output of the information switchboard, an incomplete word input to the output of the control code parity generator of the corrected information and to the output register of the read information, and a control input to the incomplete write enable output of the control unit, receive output which is connected to the control inputs of the information switch, the address switch and to the control input of the read information selector, whose information inputs are the inputs the read information of the device, and the output is connected to the input of the input register of the read information, the second output of which is connected to the input of the checker parity checker of the readout information, to the information input of the checker of the Hamming control code of the readout information and to the second input of the comparison circuit whose output is connected to the input of the decoder, the second output of which is connected to the input of the type of error of the storage unit of the accompanying information and to the input of the type of error of the block of the storage of addresses, the address input to The aux is connected to the output of the address switch, the control input is with the first control input of the storage unit for accompanying information and the output for latching the read error of the control unit, and the priority input is for the output error output of the storage unit for accompanying information and the output priority for the control unit, priority outputs recording and recording errors, the records of which are connected respectively to the input of the write error and to the second control input of the storage unit of the accompanying information, the priority input of which is connected to About the priority input of the control unit, the input of the markers and the priority input of which are the control inputs of the device, the output register of the read information is connected to the input of the driver of the parity check code of the corrected information, the error input of the RAM of the storage unit of the accompanying information is in) the devices, the outputs of the storage unit accompanying information are the outputs of the accompanying information of the device, the outputs of the address of the error of the storage unit addresses are output The device error address addresses, and the address addresses outputs — the device address addresses outputs, the output of the check code parity generator of the corrected information, and the output of the read information output register are the corrected outputs, the device information, information switch inputs of the information switch are Address switch information inputs are device address inputs. In addition, the control unit contains four OR elements, two shift registers, the AND element and the decoder, the decoder input being connected to the block priority input, the first output to the first input of the AND element, the second output to the output resolution of the block, and the first and second groups of outputs - respectively with the inputs of the first and second elements OR, the outputs of which are both the output and the second

input element AND are, respectively, the output of the block read priority, the output of block write priority, the output of incomplete block write and the input of block markers, the inputs of the third and fourth elements OR are connected to the corresponding bit buses of the block priority input, and the outputs are respectively through the first and second shifting the registers to the write error write output and the read error output of the block.

FIG. 1 is a block diagram of the device; in fig. 2 is a functional block diagram of the storage of accompanying information; in fig. 3 is a fragment of the functional diagram of the address storage unit; in fig. 4 is a functional block diagram of the control unit; in fig. 5-8 are examples of functional diagrams of a selector, a parity check code generator, a Hamming check code generator, and a read information correction block.

In tab. 1 shows the truth of the Hamming control code generator; in tab. 2 - decoding of the results. Comparison of test bits by Hammin

The control unit (Fig. 1) contains an information switch 1, which includes a group of M selectors 2 and a selector 3, an address switch 4 that includes a group of M selectors 5 and a selector 6, a control block 7, an input register 8 of the recorded information, a driver 9 parity check code of recorded information, Hamming control code generator 10 of recorded information, output register 11 of recorded information, incomplete word selector 12, read information selector 13, input register 14 of read information, form encoder 15 of the parity check code of the read information, shaper 16 of the check code for Hamming read information, compare circuit 17, decoder 18, read information correction block 19, output register 20 of read information, check parity checker 21 of the accompanying information information block, address storage 23, inputs 24 of recorded information, address inputs 25, read information inputs 26, markers input 27, priority inputs 28, control unit outputs 29-34, inputs 35-41 of the accompanying information storage unit 22, the output of the read accompanying information 42L, the output of the accompanying write information 43, the inputs 44-47 of the address storage unit 23, the outputs 48 of the memory address, the outputs 49 of the error address, the outputs 50 and 51 corrected information, output 52 of the recorded information.

The accompanying information storage unit 22 (FIG. 2) contains registers 53-57, read error input 35, write error input 36, control input 37, control input 38. RAM error input 39, priority input 40, input 41 type of error, output 42 of the accompanying information on reading, exit 43 of the accompanying information on the record.

The address storage unit 23 (FIG. 3) contains registers 58-60, counter 61, multiplexer 62, priority input 44, address input 45, error type input 46, control input 47, memory address address output 48, output 49 error addresses ..

The control block 7 (FIG. 4) contains de-blocker 63, element OR 64, element OR 65, element, AND 66, element OR 67, logical element OR 68, shift register 69, shift register 70, marker input 27, input 28 write priority priority output 29, reading priority output 30, reception resolution output 31, incomplete write resolution output 32, write error fix output 33, read error fix output 34.

The selector (Fig. 5) contains a group of elements AND 71 for two inputs and one element OR 72. The parity check code generator (Fig. 6) contains eight by the number of bytes in the 64-bit word of two modulo 73 elements 73 inputs each.

The Hamming control code generator (Fig. 7) contains eight addition elements 74 modulo two with 32 inputs each (in accordance with Table 1). The correction block of the read information (Fig. 8) contains 64 (by the number of bits in a double word) of the addition element 75 modulo two for two inputs each.

The device works as follows.

When the processors and I / O channels access the RAM, it becomes necessary to perform the following operations: writing a double word (64 information and 8 bits) into the operational memory; writing a block of information (4 double words) to the RAM; reading a double word from RAM; reading a block of information from the RAM; writing an incomplete double word to the RAM; writing an incomplete block of information to the RAM.

Record a double word. The priority signals that come in on the input; the 28 units in block 7 are scrambled by decipheror 63 and, to the servers 31, are controlled to receive a double word on register 8 through inputs 24 through switch 1 and selector 12 controlled by output 32 of block 7. The switch contains M selector 2, which are used to control the reception of information stored in the memory from the blocks of the memory management device. The selector 3 is designed to control the reception of information from the selectors 2. The shaper 9 of the parity check code of the recorded information generates the parity check bits for each byte of the information recorded on register 8. These check bits and information from the register 8 are fed to the inputs of the imaging unit 10, which forms the check bits in accordance with Table. 1. In this table, “X marked those information bits that are involved in the formation of this test bit by Hamming. The check bits from the imaging unit 10 and the information from the register 8 are fed to the inputs of the output register 11 and transmitted via buses 52 to the operational memory. Simultaneously with the described procedure for receiving a double word, the address of accessing the RAM is received at inputs 25 to the switch 4 of the address, the selectors 5 of which serve to control the reception of the addresses of access to the RAM from the blocks of the corresponding memory management device. The selector 6 is designed to control the reception of the address from the selectors 5. The selectors of the switch 4 are controlled by the signals coming in. Bus 31 from block 7. The address from switch 4 is transmitted on input 45 to register 58 of address storage block 23. The reception reception to register 58, which arrives on the bar 44 from block 7, determines to which part of block 23 the address is received and, accordingly, which RAM device is addressed. The address to the operative memory is provided by bus 48 from register 58. The correctness of the transfer of the address and the recorded data is checked in the RAM device and information about this is received by the bus 39 to the storage unit 22 of the accompanying information, where incoming bus 40, is recorded on the register 56. Recording is allowed only if there was a priority on the recording (resolution goes on bus 36). At the same time, the shift register 69 is started, which is controlled by the write operation priority signal collected on element 67 OR. After the shift register 69 counts the number of ticks needed to fix the address and data transfer error to the RAM, register 69 via bus 37 allows rewriting the contents of register 56 to register 57, from which, via bus 43, the accompanying information is transmitted to the block that made the record, indicating successful or unsuccessful completion of the operation, recording double about. words in operational memory. The procedure for writing a block of information to the operational memory basically coincides with the described procedure for writing a double word. The only difference is that not one double word is transferred to the operative memory, but four double words of the recorded data block, one step at a time. Reading a double word from RAM. The address of the requested double word is received by the servers 25 into switch 4, after which the address is transmitted via bus 45 to address storage unit 23, where it is written to register 58, where from bus 48 it is transmitted to RAM. A detailed procedure for receiving and transmitting the address to the RAM is given above in the description of the double-word write operation. In modern computers for recovery purposes. for machine error, the address of the memory location with information error must be saved until the end of the read operation. On the other hand, modern RAM devices, as a rule, have a high level of delamination. This makes it possible to access memory with a high level of overlapping operations. To ensure that both of these tasks are solved, registers 59 and 60, counter 61, multiplexer 62 are provided in address storage block 23. After setting the read priority, shift register 70 is started, which issues control signals via bus 34 connected to bus 47 of block 23 to control the rewriting of the address from register 58 to register 59, while register 58 is released to receive the address of the next address in the operative memory. After the end of the RAM cycle, the read double word through the selector 13 of the read information (the double words come from the memory on buses 26), which is controlled by the signals on bus 31, is written to the input register 14 of the read information. The selector 13 serves to receive the read data from different RAM devices. Shaper 15 generates parity check bits for each byte of the read information. These check bits and information from register 14 are fed to the inputs of driver 16, which forms check bits in accordance with Table. 1 The Hamming check bits read from the memory from register 14 and the newly formed check bits from the driver 16 are sent to a comparison circuit 17, where a fault syndrome is produced. The developed 8 bits of the error syndrome are fed to the input of the decoder 18. The decoder 18 decodes the bits with 1 error of error in accordance with the table. 2, where the symbols Si (i O-7) denote the bits of the error syndrome; the sign indicates the combination of the error syndrome bits (all are zero), in which data correction is not required; H denotes invalid combinations of error syndrome bits.

Empty cell table. 2 corresponds to a combination of error syndrome bits, which indicates an uncorrectable (for example, double) data error.

Numbers from O to 63 and the symbols Ci (i О-7) denote the data bits and the bits of the Hamming control code, respectively. With such a combination of bits of the error syndrome, there is an error in the named data discharge or control discharge.

64 outputs of the decoder 18, positionally indicating the number of the erroneous bit of data, and the data from register 14 are fed to the inputs of the read information correction block 19. The corrected information is written to the output register 20 of the read information and is transmitted from it via the bus 51 to the interrogator. The data accompanies the parity check bits generated by the shaper 21 and transmitted via the bus 50.

In order to provide the necessary depth of combination of the scans into the RAM, a block 60 and a counter 61 are provided in block 23. The address is copied to them according to signals sent by buses 47, and the address bits defining the number are written to the counter 61. double word. Thus, the address of the address is stored in block 23 for a time not less than the RAM cycle. When an error is detected in the data read from the main memory, the control signal via bus 46 prohibits writing to the register 60 and the counter 61 of the next access address. The address of the memory cell with an error through the multiplexer 62 and the bus 49 is read out as a sequential code for the purpose of recovering from a computer error.

At the same time, the accompanying information is being prepared by reading data from the RAM in block 22, which is transmitted to the interrogator along with the read data. The register 53 on the buses 39-41 is recorded with the accompanying information containing information about errors in the RAM device, the blockade interrogator number, the type of error in the read data, respectively. Write to register 53 is done when the priority of the read operation is set. The information from register 53 is overwritten to register 54, and then to register 55 via control signals received via bus 38. This provides the necessary depth of combining the reads into the read-only memory. Accompanying information is transmitted to the interrogator via bus 42.

Reading a block of information from the RAM basically coincides with the described procedure for reading a double word. The difference is that not one double word is transmitted from the RAM, but four double words of the considered data block, one step at a time. With each

Accompanying information is transmitted to the interrogator in a double word. If an error is detected in any double word of the read data block, the number of this double word in the data block is counted by the counter 61.

Write an incomplete double word. It consists of three sequentially executed procedures: reading a complete double word from the RAM, changing this double word in accordance with the record markers and information for writing, writing the newly formed double word to the RAM. The read and write output is detailed above. A double word change is made as follows.

A double word read from the RAM is sent from register 20 to the input of the incomplete word of the selector 12. To the input of the full word of the selector 12, a double layer enters, passing the switch 1 from the block that records the incomplete word. Markers

records (one marker corresponds to a specific double word byte) from the interrogator's block are received via bus 27 to control block 7, where they logically multiply by the priority signal of an incomplete word recording operation.

The named work on the splint 32 enters the control input of the selector 12. As a result, a double word composed of the bytes coming from the interrogator block (the markers corresponding to these bytes are 1) and the bytes read from the operative is written to the input register 8. memory (the markers corresponding to these bytes are 0). The operation ends by writing the generated double word to the memory.

The operation of writing an incomplete block of data to the RAM is basically the same as the procedure described for collecting an incomplete data double word. The only difference is that all the actions described are performed not on one double word, but on four double words of the block being recorded, beat by beat.

Thus, the device provides improved performance achieved by introducing tools that allow servicing requests to the RAM from multiple processors and I / O channels of a multiprocessor computer, performing independent and parallel requests for writing and reading information into the RAM, as well as the combined service of several requests for both reading and writing.

In the proposed device, in contrast to the known device, when reading information from the RAM, the operation of detecting and correcting the error is performed for each word read once. This allows you to increase the speed when reading the RAM two times.

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Claims (2)

Invention Formula L. A device for interfacing memory with a memory management device of a multiprocessor computational interface containing the input register of the read information, the first output of which is connected to the information input of the read information correction block whose address is connected to the first output of the decoder, and the output to the output register of read information, formTof / liliO i a parity check code parser of the read information, the output of which is connected to the control input of the Hamming control code generator of the read information, the output of which is connected to the first input of the comparison circuit, the control unit, the parity check code generator of the recorded information and the output register of the recorded information, the output of which is the output of the recorded information of the device, characterized in that, in order to improve speed, the information switchboard is entered into it, the switch addresses, selector of read information, incomplete word selector, address storage unit, storage unit for accompanying information, input register of recorded information, shaper of parity check code of corrected information, and Hamming control shaper of recorded information, moreover, check input of shaper form generator of recorded information connected to the output of the parity check code generator, the output to the control input of the output register of the recorded info information, and the information input with the input of the control code generator on the parity of the recorded information, the information input of the output register of the recorded information and the output of the input register of the recorded information, whose input is connected to the output of the partial word selector, the input of the full word which is connected to the output of the information switch , the input of an incomplete word is with the output of the control code generator of the parity of the corrected information and with the output of the output register of the read information, and the control The input is with the output of the incomplete write permission of the control unit, the output of which the receive permission is connected to the control inputs of the information switch, the address switch and to the control input of the read information selector, whose information inputs are the inputs of the read device information, and the output is connected to the input the input register of the read information, the second output of which is connected to. to the input of the contourJTbHOro parity code of the read information, to the information input of the Hamming control code generator of the read information and to the second input of the comparison circuit, the output of which is connected to the decoder input, the second output of which is connected to the error type input of the accompanying information storage unit and the type input the error of the address storage unit, whose address input is connected to the output of the address switch, the control input to the first control input of the storage unit of the accompanying information and in The output of fixing the read error of the control unit, and the priority input - with the input of read errors of the storage unit of accompanying information and the output priority of reading of the control unit; the outputs of write priority and of fixing write errors of which are connected respectively to the input of write errors and to the second control input of the storage unit of accompanying information whose priority input is connected to the priority input of the control unit, the marker input and the priority input of which are the control inputs of the device, the output output The read information register is connected to the input of the parity check code generator of the corrected information, the RAM error input of the accompanying information storage unit is a device error input, the outputs of the accompanying information storage unit are outputs of the device accompanying information, the address outputs of the storage address block of the address are outputs the address of the device error, and the outputs of the address of the address — the outputs of the address of the address of the device, the output of the control code generator, tnosti corrected information and output the read information output register outputs are corrected information unit, data inputs of switch information are input information recording unit, data inputs of switch addresses are addressable inputs. 2. The device according to claim 1, characterized in that the control unit contains four OR elements, two shift registers, the AND element and the decoder, the decoder input connected to the block priority input, the first output - to the first input of the AND element, the second output - from the block enable output, and the first and second groups of outputs, respectively, with the inputs of the first and second OR elements, whose outputs and output and the second input of the AND element are respectively the output of the block reading priority, the output of the block write priority, the output of the full block write and block markers input, the inputs of the third and fourth elements OR are connected to the corresponding bit buses of the block priority input, and the outputs through the first and second shift registers respectively to the write error write output and the block error write output. Sources of information taken into account in the examination 1. US Patent No. 3573728, cl. 340-1416, publ. 1971. 2. USSR author's certificate for application No. 2546739 / 18-24, cl. G 11 C 7/00, 1977 (prototype). Inputs W Inputs 25 Inputs 2ff (Pui.f 48  M fi five tch L / /    i 7 / / / f (pu.s    / 7 (rig. 7 /