SU822286A1 - Sampling device - Google Patents

Description

FIELD OF THE INVENTION technology and is intended for use as a generator of current pulses of a sample of memory devices. A selection device is known containing 1; a transformer on a core with a rectangular hysteresis loop (BCP) with two windings, a bias current source, an inductance coil connected in series with the transformer secondary winding and a bias current source, the first transistor switch connected between the beginning of the transformer primary coil and a power bus, a second transistor switch connected between the end of the primary winding of the transformer and the load, and two diodes, one of which is connected between, the beginning of the first transformer winding and power supply, and the second between the end of the same winding and zero potential bus 13. The disadvantages of this device when operating on a magnetic load (numerical ruler, sampling bus, coordinate transformer, from ferrite with BCP and so on) are low speed and high power consumption, due to the fact that the current rise time in the load is limited by the voltage power supply, and to reduce this time, an increase in the supply voltage is necessary, which increases the power consumption. The closest in technical essence to the invention is a device containing a first transistor, the base of which is connected to the first control bus of the device, the emitter to the output bus of the device, and the collector to the control winding of the transformer, the other end of which is connected to the output of the positive voltage source the cathode of the diode and with one of the terminals of the isolating capacitor, the other terminal of which is connected to the zero potential bus, to which the output winding of the transformer, the other terminal of which is connected to It is connected to the diode anode, the transformer winding is connected to the first output of the bias source, and the other end to the inductor, the other end of which is connected to the second output of the bias source, the second.

The disadvantages of this device are low speed and high power consumption, due to the fact that the current rise time in the load is limited by the supply voltage, and to reduce this time, an increase in the supply voltage is necessary, which increases the power consumption.

The purpose of the invention is to increase the speed and reduce the power consumption of the device.

The goal is achieved by the fact that a second transistor is introduced into a known device, the base of which is connected to the second control bus, the collector to the collector of the first transistor, and the emitter to the zero potential bus.

FIG. 1 shows the electrical circuit of the sampling device; in fig. 2 - time diagram of the device.

The device comprises a first transistor 1, a transformer on a ferrite core 2 with a rectangular hysteresis loop, a bias voltage source 3, an inductance coil 4, a diode 5, a second transistor 6, a bias winding 7 of a ferrite core 2, an output winding 8 of a ferrite core 2, a bus 9, potential zero, output bus 10, control winding 11 of ferrite core 2, load 12, decoupling capacitor 13, source 14 of positive voltage, first and second control buses, respectively 15 and 16.

The device works as follows.

In the initial state, in the absence of input pulses on the first and second control buses 15 and 16, the first and second transistors 1 and 6, respectively, and diode 5 are closed. A constant bias current flows through the bias winding 7 of the ferrite core 2 and the inductance 4 from the bias source 3. The voltage Uk 1 on the collector of the first transistor 1 is equal to the voltage

+ EPIT.

When a pulse (U0. A) appears on the control bus 16, the second transistor 6 opens and the preparation current flows through it and the control winding 11 of the ferrite core 2. When the total bias current field in the control winding 7 the winding 11 of the ferrite core 2 reaches the value at which the magnetization reversal of the core 2 begins, the increase in the preparation current stops due to the EMF occurrence on the windings of the core 2. In this case, the voltage Ukl on the collector of the first transistor 1 is equal to the residual voltage eniyu UQ second transistor 6. In connection with the lack of

ohmic resistance in the preparation circuit, there is no power loss in this mode and energy is stored in the windings of the ferrite core 2.

When terminating on the control bus 16 of the input pulse (Ug A), the second transistor 6 closes and the cooking current becomes zero. The ferrite core 2 begins to demagnetize, creating a positive polarity on the output winding 8. Diode 5 is opened, and the energy stored in the output winding 8 of the ferrite core 2 returns to the power source 14 (4-E f, j) and the decoupling capacitor 13.

In this case, the voltage Ukl on the collector of the first transistor 1 is equal to the emf; (created by the control winding 11 of the ferrite core. The value of E depends on the ratio of the turns of the control winding 11 and the output winding 8 of the ferrite core 2. If this ratio is, for example, one, - voltage E on the collector of the first transistor 1 will be twice as high as the voltage of the power supply + EPIT. When the input pulse Ug is input to the control bus 15, the First transistor 1 opens and through this transistor and control winding 11 fe because the voltage drop across the first transistor 1 is small, the rise time of the sampling current in load 12 is determined by the voltage E on the collector of the first transistor 1, the value of which is twice the supply voltage + TU (, - T and provides a rapid increase of the current in the load 12. At the same time, the supply voltage + TPS "T can be reduced by 30-40% with the same sampling time, which ensures a reduction in power consumption. The sampling current increases exponentially, while simultaneously the voltage Ukl on the collector of the first transistor 1 decreases. When the total field: displacement in the bias winding 7 and the sampling current in the control winding 11 of the ferrite core 2 reaches the value at which magnetic reversal of the core. 2, the current rise in the sample is stopped. In this case, the amplitude of the sampling current is proportional to the bias current and does not depend on the supply voltage + EPIG, the voltage Ukl on the collector of the first transistor 1 becomes equal to the drop in voltage Uk on the discharge 12.

When the input pulse Ug terminates on the control bus 15, the first one, transistor 1 closes, the current of the sample becomes zero and the energy stored in the output winding 8 of the ferrite core 2 returns to the power source 14 (+ EPIT)

The proposed device, as compared with the known, provides a positive effect, consisting in increasing the sampling time of the current in the load by 30-40% by increasing the voltage on the collector of the first transistor 1 at the time of forming the leading edge of the sampling current and reducing the current consumption of the device by 30-40%, since the voltage of the power source 4-Ef, j, T can be reduced while maintaining the sampling current rise time in the load.

Claims (2)

Invention Formula The sampling device containing the first transistor, the base of which is connected to the first control bus of the device, the emitter to the output bus of the device, and the collector to the control winding of the transformer, the other end of which is connected to the output of the positive voltage source. the cathode of the diode and one of the terminals of the coupling capacitor, the other terminal of which is connected to the zero potential bus to which it is connected. Holiday & the transformer winding, the other output of which is connected to the diode anode, the transformer sweeping winding is connected to the first output of the bias source, and the other end to the inductance coil, the other end of which is connected to the second output of the bias source, the second control bus, characterized in that in order to increase speed and reduce the power consumption of the device, it contains a second transistor, the base of which is connected to the second control bus, the collector -. to the collector of the first .histor, and zmitter -.k to the zero-potential bus. Sources of information (), taken into account in the examination 1, Patent of Great Britain 1341498, cl. 43 B (NRT), published, 1973. 2. USSR author's certificate J 577563., cl. G 11 C 7/10, 1976 (prototype). .A i / h.B (put.l