SU817603A1 - Phase shift-to-digital code converter - Google Patents

Description

one

This invention relates to measurement.

electrical quantities and is designed to convert the phase shift of a sinusoidal signal into a digital code,

Known transducer phase shift into a digital code containing the reading device, the distributor, electronic switches, phase shifters and. phase sensitive detector l.

A disadvantage of the known device is the inadequate speed and accuracy.

The known device for measuring phase shift, which includes a phase shift transducer into a digital code, consisting of limiter mixer, counter, phase sensitive element, pulse generator, frequency dividers and digital reading device 2.

The drawbacks of the device are low resolution and accuracy due to the influence of higher harmonic components in the signals of the frequency dividers, as well as the sequential input of pulses into the frequency dividers, which limits its speed.

The purpose of the invention is to increase the points. performance and speed.

The purpose of the invention is achieved by the fact that a phase shift converter into a digital code, comprising a pulse generator, the first and second outputs of which are connected respectively to the inputs of frequency dividers, is equipped with a summation unit synchronous

0 by the detector, the first and second shapers, controlled by a pulse generator, a control unit of a sign, a reversible counter, a valve unit, the first AND second code-converter, the first output of the first frequency divider is connected to the first shaper through the first shaper valve block, and its second output is connected to the input

0 of the first code-voltage converter, the first output of the second frequency divider is connected to the first input of the synchronous detector via the second driver, and the second output through

5, the second code-voltage converter is connected to the input of the adder, the output of which is connected to the second input of the synchronous detector, the output of which is connected through a control unit of the sign and a controlled oscillator

pulses, respectively, with the first and second inputs of the reversible counter whose output through the valve block is connected to the second input of the second frequency divider.

The drawing shows a block diagram of a phase shift converter to a digital jBpft code.

The phase shift to digital converter contains a block 1 summation, the first converter 2 codes to a sinusoidal signal, a synchronous detector 3, the first driver 4, a controlled pulse generator 5, a reversible counter 6, a sign control unit 7, a pulse generator 8, the first and second dividers 9 and 10 frequencies, the second converter 11, the code voltage, the second driver 12, and the valve block 13.

The device works as follows.

The input sinusoidal signal U of the unknown phase f is fed to one of the inputs of summation unit 1, to the second input of which a compensating signal I2 is fed from the output of converter 2 of the code to voltage. The output from the output of the summation unit 1 is fed to the input of the synchronous detector 3. The second input of the synchronous detector 3 is fed through the shaper 12, the phase of the first harmonic of which is shifted

by angle J relative to the voltage phase Ug. The constant voltage component at the output of the synchronous detector 3, proportional to the phase difference between voltages 1) 2 and U, is converted to a proportional pulse frequency controlled by the generator 5 and to logical signals to control the counting sign of the reversible counter 6 into the sign control unit 7 . A reversible counter 6, depending on the sign of the phase difference between voltages and 112, adds or subtracts the pulses of the controlled oscillator 5,

The pulses from the generator 8 of the high-frequency pulses F are constantly summed up in the dividers 9 and 10 frequencies, the output frequencies of the last triggers in which are equal to the frequency f of the input voltage. The frequency divider code 9 is fed to the input of the functional converter 2 codes into sinusoidal voltage and to the input of the imaging unit 4, which generates frequency pulses at the moment the state of all the triggers of the frequency divider 9 changes from a logical unit to a logical zero. The code recorded in the reversing counter b, through the valve block 13, impulses from the generator 4 to the installation inputs of the frequency divider 10, setting in the latter a number equal to the number M in the reverse

counter 6, thereby shifting in phase the constantly changing frequency divider code 10 with respect to the constant varying code of the trigger divider 9 by an amount proportional to the AND number in the reversible counter 6.

Thus, the sinusoidal voltage from the converter 11 connected to the outputs of the frequency divider 10 is shifted in phase relative to the sinusoidal voltage from the output of the converter 2 by an amount proportional to the M number recorded in the reversing counter 6. The reversible counter b adds, or subtracts, pulses from generator 5 is controlled as long as voltage Ug. from the output of the functional converter 2 will not become in phase with the input voltage Uy, the constant component of the voltage at the output of the synchronous detector 3 is zero and the flow of pulses from the controlled generator 5 to the input of the reversible counter b stops. The code in the reversible counter b when the constant component at the output of the synchronous detector 3 is zero equals the phase shift between the input voltage U and the reference Uon

Any change in the phase of the input signal U causes the appearance of a constant component at the output of the synchronous detector 3, the appearance of pulses at the input of the reversible counter b, a change in the code in it, a time shift of the constantly varying code of the splitter 10 frequency relative to the splitter code 9 frequency and, accordingly, a change in the phase of the compensating voltage Uj, until the code in the reversible counter b corresponds to the new value of the phase difference between the input and and reference and „p voltages.

The sequential inclusion of an adder with a synchronous detector allows one to eliminate the influence of higher harmonic components on the accuracy of converting the phase shift into a digital code. An increase in beat velocity is provided by parallel input of a number from a reversible counter at the signal of the first frequency divider. The use of a controlled oscillator ensures linearity and increases the range of permissible rates of change in the phase of the input signal.

Claims (2)

1.Smirnov P.T. Digital geometers L., 1974, pp. 8-10. 2. Authors certificate of the USSR 245914, cl. 01 R 25/00, 1968. f, fzh