SU813493A1 - Device for displaying information on crt screen - Google Patents

Description

The invention relates to automation and computer technology and can be used in devices designed to display graphical information on a screen of an electron-beam tube (CRT. A device is known that contains a vector generator connected to linear coordinate amplifiers connected to a deviation of the CRT system 1 The disadvantage of this device is its insufficient speed. The closest to the present invention is a device containing sequentially connected vector generator and Amplifiers, each of which consists of a preamplifier, direct current amplifier, a terminal amplifier connected to the deflection of a coil of voltage dividers, connected to the output of a terminal amplifier, comparators, whose inputs are connected to voltage dividers, and outputs to control inputs of keys, connected to the power sources of the final amplifier 2. The disadvantage of this device is the low image quality. The purpose of the invention is to improve the image quality by eliminating non-linearity Yeni beam. The goal is achieved by the fact that the device contains a vector generator, the inputs of which are. connected to the outputs of the registers of the increments of codes by the X and Y coordinates and the register of the vector module, the outputs of the vector generator are connected to the inputs of the preamplifiers, the outputs of which are connected to the inputs of the final amplifiers connected to the power supply sources, the outputs of the final amplifiers are connected with deflecting coils of a CRT, a decoding unit is introduced, the inputs of which are connected to the outputs of the registers of increments of codes along the X and Y coordinates and the module of the vector, and its outputs - to the control 1ltsim inputs of the key elements; and the fact that the decoding unit contains a serially connected divider and decoder, the inputs of the divider are connected to the inputs of the block, and the outputs of the decoder to the outputs

block, and the fact that the decoding unit contains the first shift register, the inputs of which are connected to the inputs of the block, and combinational decoders, each of which consists of a shift register, the inputs of which are connected to the inputs of the block, and the outputs to the inputs of the first, second, third of the elements NOT and the first input of the first, second elements NAND, the output of the first element is NOT connected to the second input of the first element. AND-NOT and the first input of the third element AND-NOT, the second input of which is connected to the output of the second element NOT, the outputs of the first and third elements are connected to the inputs of the element OR-HEf whose output is connected to the input of the fourth element NO, the output of which is connected to the second input of the second element AND-NOT and the first input of the fourth element AND-NOT, the second input of which is connected to the output of the third element NOT, the outputs of the second and fourth elements are connected to the outputs of the block, while the outputs of the first shift register are connected to the third and fourth mouth inputs of first AND-NOT combination of each decoder.

FIG. 1 is a diagram of the device in FIG. 2 and FIG. 3 - diagrams of two options for constructing a decoding unit.

The device contains registers 1 and 2 of increments of codes along the X and Y coordinates, register 3 of the vector module, 4 vector generator, decoding unit 5, preamplifiers 6 and 7, terminal amplifiers 8 and 9, key elements 10-13, isolating elements 14 and 15, power supply sources. Decoding unit 5 (FIG. 2 may be made in the form of a serially connected divider 20 and a decoder 21. Another variant of the construction of the decoding unit is shown in Fig. 3. The decoding unit contains a first shift register 22 and combinational decoders 23 and 24, each of which consists from the shift register 25, elements 26-29 NOT, elements 3033 AND-NU, element 34 OR-NOT. The positions 35-37 denote the inputs of the decoded unit, the positions 38-41 of its outputs.

The device works as follows

. In the absence of a signal at the inputs of the preamplifiers B and 7, the final amplifiers 8 and 9 through the isolating elements 14 and 15 are powered from sources 18 and 19 of low voltage.

In order to form a sawtooth current, the deviations of the EL beam to the deflecting coils of the CRT (not shown, it is necessary to apply constant

the magnitude of the voltage drops from the outputs of the final amplifiers 8 and 9. The amplitude of the voltage drop is determined by the steepness of the input saw-tooth voltage; In the case when vector shaping is performed at a constant recording speed, the slope of the sawtooth voltage and, consequently, the voltage drop amplitude at the output of the final amplifiers 8 and 9 are a function of the angle of the vector relative to the coordinate axes and does not depend on the length vector Therefore, the value of the steepness of the sawtooth voltage for each coordinate can be determined even before

5 start the formation of a vector by calculating the relationship

Nux

Nav

cJv NM NM

If the vector is parallel to one of the coordinate axes, then N is equal to the increment code of the given coordinate and S 1. In this case, the output amplitude

The voltage of the terminal amplifier is maximum at this coordinate. At intermediate positions of the vector, the amplitude of the output voltage of each of the final amplifiers 8 and 9

P takes a value from a maximum to 0. Therefore, in order to minimize the power dissipated by the final amplifiers 8 and 9, it is necessary depending on the value), in some way or other, the voltage value should be changed

powering all amplifiers so that the difference between this voltage and the output voltage of the amplifiers is minimal.

Dp this when forming the next vector increment codes

from registers 1 and 2 and code

N

N & y

Yes

the module of vector N from register 3 enters the generator of 4 vectors and decoding unit 5. The latter produces a calculation, and b, thereby determining the relative steepness of the input voltage of preamplifiers 6 and 7. The values of the ratios obtained in binary code

0 S is decrypted, and the logical signal at the corresponding output of the decoder is then used to turn on each coordinate with the power of one of the keys 10-13 of the power sources, corresponding to the sign and slope of the input voltage of the preamplifiers 8 and 9. Building a decoding unit by It is advisable to use the second variant (FIG. 3) with a small number of power sources, which is the case in the overwhelming number of cases of practical implementation of the device.

Claims (2)

1. US patent 3430207, CL. 340-172.5, 1972. 2. US patent number 3725897, CL. 340-324А, 1974 (prototype). 37 38