SU813456A2 - Analogue-digital integrator - Google Patents

Description

one

The invention relates to automation and is intended to form a voltage proportional to the integral of the input signal. It can be used in systems for the automatic regulation of various technological processes, as well as objects that have large time constants.

 According to the main auth. No. 507872 is a known analog-to-digital integrator, which contains a voltage-frequency converter with an analog integrator, a reversible pulse counter, a digital-analog converter, an output adder, and a circuit for recording initial conditions and recovering information with comparison, selection module, tracking-storage units and a switch connecting the tracking unit. - storage to the output of the analog-digital integrator or to the source of setting the initial conditions depending on the operating mode of the integrator}. :

However, the use of the known analog-digital integrator for a considerable time without maintenance is difficult due to the lack of integrator control circuits in it, which can lead to a failure. Lack of health monitoring also eliminates the possibility of automatic commissioning of an integrator that is in cold standby, which is highly desirable to increase the reliability of control systems.

w The purpose of the invention is to increase the reliability of the result by providing an automatic monitoring of the integrity of the integrator. This goal is achieved by the fact that a filter, a differentiating circuit, a series-connected aperiodic filter, a key and a relay element, a pulse generator, delay lines, limiting resistors, and two AND elements, the first

0 inputs are connected to the corresponding outputs of the delay line, the second inputs of the And elements are connected to the pulse generator and the reset input of the relay element, respectively, and the outputs of the And elements are connected to the meter installation buses, and the key input is connected through the series-connected first limiting resistor and filter

0 with an aperiodic filter input and

the output of the comparison unit and through the second limiting resistor, c. the output of the tracking-storage unit, the control input of the key is connected via a differentiating circuit to the output of the allocation module of the module, the input of the delay line is connected to the output of the higher digit of the counter, and the input of the relay element via the third limiting resistor to the operational amplifier.

Fig, 1 shows the analog-digital integrator; 2, time diagrams of his work in the control mode.

The analog-to-digital integrator contains a voltage-frequency converter 1, built on an analog integrator 2 with a circuit 3 reset to zero state and a three-position comparator 4, a counter 5 with inputs 7 and 8 of the reverse control, a digital-analog converter 9, an output adder 10 with scale resistors 11 and 12 and a control key 13 on a transistor connected via a matching circuit 14 to a comparator pulse output, a two-position switch 15 with inputs 16, 17 and a control input 18, block, 19 tracking-storage, containing usi rer 20, - a storage capacitor 21, the source follower FET 22 and the switch 23 tracking-mode storage unit 24 comparison, a resistor 25, separation unit 26 and modulation .element logical AND-NO element 27,

To the analog-to-digital integrator 28 formed by the indicated elements, an aperiodic filter 29 is additionally connected to the operational amplifier 30, resistors 31, 32 and capacitor 33, a switch 34, a relay element 35 having a reset input 36, a self-blocking circuit and a zero position, the generator 37 pulses, a delay line 38 and two elements 39 and 40, a key input 34 through limiting resistors 41 and 42 are connected respectively to the outputs of the aperiodic filter 29 and the tracking-storage unit 19 and through the limiting resistor 43 and the filter 44 on the cond The sensor 45 and the resistor 46 are connected to the input of the aperiodic filter 29 and the output of the block 24 is compared. The control input of the switch 34 is connected to the output of the module allocation module 26 via a differentiating circuit 47, the input of the relay element 35 is connected to the summing point of the amplifier 30 through a resistor 48,

The analog-digital integrator operates as follows. In the intervals between the control intervals, if the input signal Ug is present, the frequency voltage converter generates pulses with a frequency proportional to / Ufex /. Let, then, on the potential outputs of the three-position comparator 4 connected to control inputs 7 and 8, the reversible counter 5, sets the voltages setting the counter on the addition of pulses. The code combinations that occur in the meter are converted by the digital-to-external converter 9 to the increasing voltage, which is fed to the input of the adder 10. The appearance of pulses on the counting input 6. reversible counter 5 occurs at times when the voltage at the output of the analog integrator

5 2 reaches the trigger level of the comparator 4, after which, under the action of the output signal of the KONtnapaxopa, the analog integrator 2 is quickly reset (capacitor discharge). As a result, the comparator 4 is turned off and the charge of the capacitor under the action of Utx- is repeated. Therefore, for each period of operation of the converter 1 in the counter

5 5 fixes the increment of the integral voltage Uyi, i.e. the quantization of the input voltage integral Ubx occurs. by level. To eliminate quantization error in

 the circuit performs a summation of the output signal of the digital-to-analog converter 9 with the output signal of the analog integrator 2 using an adder 10. Elimination

voltage spikes at the output of the analog-to-digital integrator arising at the time of resetting the analog integrator 2 are achieved using resistors C, 12 and a switch 13 on the transistor, the base of which

0 through the matching circuit 14 is connected to the pulse output of the comparator 4, whereby the adder 10 is disconnected from the analog integrator 2 during the discharge of its capacitance,

5 With a single signal Uy, the switch 16 is in a position in which the output of the analog-to-digital integrator is connected to the input of the tracking-tracking unit 19. This block

0 in the absence of a counter counter 5, it operates in the tracking mode for the output voltage of the integrator.

24 comparisons act practically

equal voltages Oi and iy, and therefore the output signals of comparator unit 24 and module allocation unit 26 are zero. A single signal occurs at the output of the NAND gate 27, supporting the switch 23 in the closed position, which corresponds to the tracking mode of block 19. Note that in this case the comparison block 24 does not affect 65 the operation of voltage-frequency converter 1, since the current through resistor 25 is zero.

The process of integrating the negative voltage Ox. flows in the same way as in the case of a positive voltage Utox, with the only difference being that under the action of i ". A reversible counter 5 is adjusted by the comparator 4 to subtract the pulses arriving at its counting input 6. As a result, the voltage TJtH at the integrator output decreases.

During the operation of the device in the integration mode of the input voltage Ubx f due to the absence of a signal at the output of the comparator unit 24, the voltage at the output of the aperiodic filter 29 and to the capacitor 45 of the filter 44 are zero. Therefore, only the OUTPUT signal of the storage tracking unit 19 is fed to the input of the key 34. This signal is not transmitted to the input of the relay element 35, since the key 34 is closed because the voltage at the input of the differentiating circuit 27 does not change. In the absence of generator pulses 37, the outputs of the elements 39 and 40 are affected by zero logic signals that do not affect the operation of the reversible counter 5.

We now consider the integrator in the control intervals. The output pulse ie7 of the generator 37, depending on the state of the sign trigger in the higher discharge of the counter 5 and, accordingly, the signals at the output of the delay line 38, through the elements 39 or 40 enters one of the buses of the installation of the counter 5. If by the time of the occurrence of a pulse Uj code in the counter exceeded zero value (the output voltage of the integrator) (diagram A in Fig. 2), then the impulse Ujf code in the counter takes the minimum value (-Nmon). At (- diagram B in Fig.), the generator impulse passes through the element 40, and the counter is set to ma The xyms code (+ Ni1In) of the normal operation of the circuits of the installation of the counter, the delay time of the line 38 should exceed the pulse duration and $ 7. At the same time, the pulse and 37 is fed to the input 36 of the relay element 35, setting it to the zero position, in which the fault signal UCH is absent. At the end of the generator pulse 37, which keeps the counter 5 in the state of maximum or minimum code, the integrator enters the information recovery mode. Under the action of the difference between the signals at the outputs of the adder 10 and the tracking-storage unit 19, the comparison unit 24 generates a voltage that, through the module selector 26 and the NAND gate 27, switches the switch 23 to the open state. At the same time, the storage tracking unit 19 goes into storage mode and, at its output, holds the output voltage of the integrator, prior to setting the counter 5 to the maximum or minimum code position. When the comparator unit 24 is triggered, a negative feedback loop is closed, covering the English-digital integrator. When the resistance of the resistor 25 is sufficient, the output voltage of the comparison unit 24 prevails over the input signal Ubx./ and due to the deep negative feedback, the integrator is fast enough. unloads the voltage U. As a result, the source code is restored in the counter 5, and the voltage at the output of cynwaTopa 10 takes a decrease almost equal to Un. After that, the signal at the output of the comparator unit 24 assumes a zero value, the switch 23 is set to a closed position,. the tracking-storage unit 19 goes into tracking mode for the output and voltage of the adder 10, and the integrator continues to integrate the input signal.

The duration of the information recovery interval is determined practically by the time during which the output voltage of the sum of 5 .tor 10 varies by the value (UnJ + (Uw, aA where ((and, oo)) Const is the absolute value of the voltage, corresponding to the maximum (Nmox) or minimum (Nm, n) code.

0 recovery time Tvoss. the capacitor 45 of the filter 44 is charged to the voltage U at the output of the comparison unit 24. Therefore, the recovery time

Un) + (UmQX)

 (one),

tons of places

(Ui4)

where Tt) is the constant integration of the analog-to-digital integrator in the course of information recovery. The constant constant is connected with the main constant of integration by the ratio

GH.EDU:, G,

where R is the resistance on the main

integrator input.

Under the action of voltage U

capacitor charge also occurs

33 of the aperiodic filter 29, and its output voltage varies

according to law

29 (- UM + UO) d-e)

(2)

31

where Ug is the initial voltage at 65 capacitor 33; R and Rjj. - the resistance of the resistors 31 and 32 fjy is the constant of the filter time (Cpz) - the capacitance of the capacitor 33.

Due to the presence of a differentiating circuit 47, the output voltage of the module allocation module 26 is not supplied to the gate of transistor switch 34, and the notoiviy aperiodic filter 29, filter 44 and tracking-storage unit 19 are disconnected from the input of the relay element 35,

With a sufficiently large amplification factor of the operational amplifier 30, the voltage at its summing point is almost zero and does not affect the state of the relay element 35. As a result, in the process of restoring information, the relay element 35 remains in the zero position.

If the time constant of the aperiodic filter 29 Gg satisfies the conditions (T L7 - period of the generator 37) and T 29 T, then the initial finding of U o on the capacitor 33 is zero, and after decomposition e - t / tjg in a row will get

„T hossg.

W - Кз - Сэ, «f3) Substituting in (3) the value of T ос const from (1), we find the voltage at the output of the aperiodic filter at the end of the recovery time

, 1Ud1x-1 ± (t.

Uz9 (TboccT) - to „. Сз7 If you choose Кз1Сза TV, then Ul9 (Thy) - (/ UmQx / + / Uh /) (4)

From (4), it follows that in a working analog-digital integrator, the output voltage of the aperiodic filter at the end of the recovery time T B is equal to the total voltage variation at the integrator output (adder 10) during the information recovery time.

At the end of the recovery time, a voltage drop Uj occurs at the output of the module allocation unit 26, as a result of which a negative pulse arrives at the gate of the field-effect transistor 34 through the differentiation circuit 47, opening the transistor 34. At the input of the relay element 35, the output voltage is compared aperiodic filter 29 with voltages on the capacitor 45 and at the output of the tracking-tracking unit 19. The voltage Uj at the input of the relay element 35 is proportional to the difference

U59- (Uv, + U44).

If the duration of the TCP comparison time, during which the transistor 34 is open, is sufficiently small, then during the time Ter capacitors 44 and

33 do not have time to discharge -. Consequently, UjV (TCP) and, 9 (Tgst) and (Ter) i.

Therefore, the resulting signal at the input of the relay element 35 in the comparison interval is almost zero (lies in the dead zone of the relay element +}, and the fault signal UCH is absent.

It is obvious that almost any malfunctions of the analog-digital integrator lead to a change in its constant integration and violation of the equality Rj-C t ,, which ultimately causes a change in the recovery time of the information. As a consequence, the output voltage of the aperiodic filter 29 will differ from the value defined by the expression (4). As a result, a voltage imbalance at the inputs of the relay element 35 occurs in the comparison intervals Ter, which leads to its activation and the appearance of a fault signal UCH.

Due to self-locking of the relay element 35, the fault signal is preserved until the next monitoring pulse arrives from the generator 37. After that, the relay element is reset to the zero state and a new control cycle begins, during which the signal UCHg is generated again if the fault remains unresolved.

If you accidentally reset counter 5, the process of restoring information 5 is the same as in the case discussed above. Since the information recovery time in case of failure is different from the value determined by expression (1), a differential voltage appears at the input of the relay element 35 upon completion of the recovery process (when the switch 34 is closed). Under the action of this voltage, a malfunction signal is generated, which is maintained at the output of the relay element 35 until the next pulse of the generator 37 arrives. However, unlike in the case of integrator malfunction, the UCH signal will not be acknowledged in case of a random failure.

Note that a significant part of the failures of the analog-digital integrator makes it impossible to recover information in the counter. However, after the arrival of the generator 37, the changing state of the counter 5, the outputs of the comparison and allocation modules 24 of the module 26 remain constant for a long time.

60, as a result, the key 34 remains in the open state and the aperiodic filter 29, the capacitor 45 and the storage tracking unit 19 are disconnected from the relay element. For

65 the occurrence of these failures is

The connection of the input of the relay element 35 with the summing point of the aperiodic filter 29. If the operating time of the voltage U at the input of the filter 29 is sufficiently long, the operational amplifier 30 goes into a saturation state, and a voltage exceeding the threshold appears at the summing point of this amplifier actuation of the relay element 35, signaling failure.

Thus, due to the specified elements and connections introduced into the analog-digital integrator circuit, the integrator can be automatically monitored by periodically setting the counter to a predetermined state and monitoring the information recovery time.

The proposed scheme allows detecting both gradual failures associated with a change in the constant integration, as well as failures that lead to a complete loss of the integrator's performance.

Claims (1)

1. USSR author's certificate 507872, cl. G 06 G 7/186, 1973, (prototype).