SU732905A1 - Analog-digital integrator - Google Patents

Description

one

The device is about-gaosits to automation and is designed to form a voltage, which is a process integral of the EXIT. signal. It can be used in systems of automatic control of various objects when large constant integrations are required.

Analog-to-digital integrators are known that contain a voltage-to-frequency converter connected in series, a reversible pulse counter, and a cyro-analogue converter Ij.

The disadvantage of such integrators is low noise immunity, since meter failures under the influence of interferences and interruptions in the power supply (due, for example, to automatic switching from the main supply network to the backup network) cause destruction of the information accumulated by the integrator, which can lead to emergency consequences, and therefore, in many cases, it is completely unacceptable. Moreover, these 1 lines do not provide automatic recording.

initial conditions, which makes them difficult to use in control systems.

The closest technical solution to the proposed one is an analog-to-digital integrator 2, which contains series-connected voltage-to-frequency converter, a reversible pulse counter, a digital-to-analog converter with an output amplifier, a switch whose other input is connected to an initial condition source, tracking unit-storage unit of the battle, connected by another input to the output of the D / A converter, and the unit

15 allocation module, the output of which is connected to the input of the frequency adjustment of the voltage to frequency converter and through the IS-NOT element to the control input of the tracking-storage unit.

20

This integrator does not work accurately for short breaks. The purpose of the invention is to improve the accuracy of the integrator during short power interruptions. The goal is achieved by the fact that an analog-digital integrator containing two sources of voltage of opposite polarity and a series-connected first switch, the first information input of which is the information input of the integrator, voltage-to-frequency converter, reversible pulse counter, digital analogue converter, the output of which is the output of the integrator, the second switch, the other information input of which is the input of the initial conditions of the integrator, block and - storage, the comparison unit, connected by another input to the output of the D / A converter, and the allocation unit of the module, whose input is connected to the second information input of the first switch, and the output connected to the control input of the first switch, to the frequency converter input A peak detector, a power supply voltage detector and a time relay are introduced into the frequency and to the first input of the NAND element connected by the output to the control input of the tracking and storage unit according to the invention. The relay output is connected to the second input of the NAND element and to the control input of the second switch; a time relay input is connected to a positive polarity voltage source and to a peak detector input. The detector output is connected to the first auxiliary input of the monitoring unit, and to the power input of the power supply voltage detector connected to the second additional node of the tracking storage unit. Two groups of inputs of the power voltage detector are connected to two main and a group of additional sources of positive and negative polarity. The power supply voltage detector contains an output cascade on two transistors of different conductivity types, the output of which is the output of the mash signal, two groups of EOSODUS transistors of different conductivity type and two groups of voltage dividers formed by series-connected stabilizers and resistors and connected inputs to the corresponding alarm inputs. The outputs of the voltage dividers are connected to the bases of the corresponding input transistors of various types of conductors, the emitters of which are connected to the zero potential bus, and the collector; connected to the input of the output stage. The tracking-storage unit contains an operational amplifier, the circuit between the inverting input and the output of which includes a double-ended suppressor and a storage capacitor connected in series, a MOS transistor connected by a gate and a substrate to the additional inputs of the unit, and the first limiting resistor. Between the inverting input of the operational amplifier and the input of the unit, a serially connected normally closed key and a second limiting resistor are connected, and between an inverting input of the operational amplifier, a third limiting resistor and a normally open switch, connected to the control input of normally closed, are connected to a zero potential to the zero potential key and with the utflaval input of the block, the node connecting the first limiting resistor to the MOS transistor is the output ohm block. FIG. 1 is a functional diagram of the analog-digital integrator in FIG. 2 - time diagrams that show his work. The integrator contains the first switch-over unit 2, the voltage-to-frequency converter 3 with the differential pulse output and the frequency tuning input 4, the reversing pulse counter 5 with the pulse inputs of addition 6 and subtraction 7, the digital-to-analog converter 8, the second switch 9, the other input of which is connected to the source 1O of the initial conditions of the integrator, the block next to NIN-storage 11, performed on the operational amplifier 12 with a storage capacitor 13 in the negative feedback circuit and a normally closed key 14 between the inverting input and the summing point to which the input resistor 15 and the feedback resistor 16 are connected, a comparison unit 17 and a module 18 of the allocation unit, the output of which co-i is single with the control input of the switch 2 and c one of the inputs of the element 19, the other input of which is connected to the control input of the switch 9, and the output is connected to the control input of the normally closed switch 14. The storage capacitor 13 is connected to the output of the operational amplifier 12 through the series-connected MOS-transponder The resistor 20 and the limiting resistor 21, the inverting input of the operational amplifier 12 is connected to the zero potential bus through a series-connected limiting resistor 22 and a normally open switch 23, the control input of which is connected to the u-input of the IS 19 element. amplifier 12 is connected to symmetry. and a resistor 24, and in the back feedback circuit of amplifier 12, includes a non-linear element 2 5, which is made according to the circuit of two-sided limiting of the output voltage of the amplifier. The analog-digital integrator also contains two voltage sources 26, 27 of opposite polarity, a peak detector 28, a power supply signaling device 29 with an output transistor ZO, the emitter of which is connected to the first power supply point 26, and a time relay 31 with the time setting RC- circuit on Vkok (resistor 32 and capacitor 33) and a hysteresis relay element 34 at the output, and in parallel with time the driving capacitor 33 is connected in parallel to the diode 35 and the resistor 36. The collector of the output transistor 3Q is connected The output of the peak detector 28, as well as the gate of the MCfI transistor 20, the substrate of which is connected to the output of the peak detector 28. The input of the peak detector 28 and the time setting resistor 32 are connected to the voltage source 27, and the output of the hysteresis relay element 34 is connected to the input input of the switch 9, the signaling device 29 of the supply voltage, along with the output transistor 30, contains a transistor 38 of a different conductivity type, resistors 39-41, input p-g - p-transistors 42, 43 and pn-p-transistor 44 The collectors of transistors 42-44 are connected to The base of the transistor 38, the emitters are connected to the zero potential potential, and the bases are connected to the outputs of the voltage dividers formed by the zener diodes 45-47 and the 485O resistors. Voltage dividers are connected between sources of opposite polarity in this way. that the base of the acou / circuit p-and-p trlnz1ktora 43 is connected to the anion of the zener diode, which is connected to a source of positive polarity, and the base of the input pnp-transistor 42 is connected to the power bank of the zener diode, the anode of which is connected to the source of the voltage is negative. In addition to the power sources 26 and 27 and the power source 51 (of positive polarity), there may be more secondary power sources. since their number is determined by the TiffloM applied in the integrator of functional units and the requirements of their supply chains. . Nonlinear element 25 can be formed by zener diodes 52, 53, diodes 54, 55, and resistors 56, 57. The inerter can work in 1degeneration modes, recovering information from meter failures, recording nachapngy conditions and restoring gyrations, after short interruptions in power supply, In the 1v Integrated mode, the device operates after the termination of transients in the power circuits and the time relay 31 is turned on. when the voltage on the capacitor 33 of the SC,) exceeds the response level of the nestled relay element 34 and the output signal of the relay has a single value. On this signal, the switch 9 connects the input of the tracking-storage unit 11 to the output of the digital-to-analog converter 8. In this case, the input voltages of the power sources 26, 27, 51 are nominal, the input transistors 42-44 of the voltage detector 29, the transistors 38 and The DA is open, as a result of which the MOS transistor 2O is in the open state and connects the storage capacitor 13 through the resistor 21 to the output of the operational amplifier 12. The initial state of the information recovery circuit, in the tracking unit - storage 11, the comparison unit 17, the module 18 allocation module and the element IS-NOT 19, corresponds to the equality of the absolute values of the output voltages of the cy-analogue converter 8 (tracking block-storage 11 (the output voltage of the module 18 allocation module 18 has zero value, and a switch 2 connects the input of a voltage to frequency converter 3 with an input source and an element. AND-HE 19 holds the key 14 in a closed state and the tracking unit 11 operates in a voltage tracking mode If present input signal a ((D) converter 3 to a frequency voltage generates pulses with a frequency f, proportional to U, which depending on the sign ,, and to the inputs of adder subtractor 6 or 7 input down counter 5 pulses. For each period of operation of the converter 3, the magnitude and sign of the increment of the integral of the input voltage, i.e. the input level integral is quantized by level. Thus, in the counter 5, a digital code N is generated, which characterizes, which with the help of the digital-to-analog converter 8 is converted into an equivalent electrical gain. During normal operation of the analog-digital integrator (without meter failures), the tracking unit is stored; ESH is in the mode of tracking the output signal, and the tracking speed selects

c is higher than the maximum rate of change of C y, and the dead band of the comparison block 17 is not less than one quantum

SignalC

lg, yx, and the recovery circuit are in the initial state. If the integration process (or the storage of the integral O) fails to counter 5, then due to the limited tracking speed of the tracking unit 11, the signal at the inputs of the time block will differ by Led 1 reason, exceeding his zsiu sensitivity. Hat the output of the comparison block 17 produces a voltage, the sign of which is determined by the matching of the signals and and. In this case, the module allocation module 18 generates, regardless of the sign of the error signal, | iUp is the single value of the logical signal, according to which the element 19 switches the key 14 to the open state, and the tracking-storage unit 11 goes into the voltage maintenance mode and, prior to the counter, 5) the storage mode). Simultaneously, according to the signal of the module 18, the module 2 switches the input of the voltage-frequency converter 3 to the output of the comparison block 17. Under the action of the signal from the comparison block 17, the converter 3 restores the information in the counter 5, since the pulses are fed to one of the counter inputs until the difference

Claims (2)

To reduce the integrator error in this mode of operation, a limiting resistor 22 and a normally open switch 23 are also entered into it. When the voltages and gjj, and U do not decrease the value at which the comparison unit 17 will turn off. takes a zero value, and therefore, switch 2 connects the input of converter 3 to the source Ug, switch 14 is closed, and the tracking unit-storage goes into tracking mode Ugy, and the circuit returns to its previous state, ensuring The willow further formation of the integral from the input signal of the TIDI. In order to reduce the integrator error associated with the potential change on the storage capacitor 13 during the operation of the tracking-storage unit 11 in the storage mode, it is necessary to increase the frequency of the converter 3, i.e. reduce recovery time information. For this purpose, when the comparison unit 17 converter 3 is triggered by a signal from the module allocation unit 18, inputted to input 4, is tuned to an increased pulse frequency {((, tracking-storage unit 11 operates in tracking mode, the switch 23 is open and balancing equivalent resistances at the inputs of the operational amplifier 12 is ensured by the fact that the resistance of the resistor 24 is chosen to be equal to the resistance of the parallel-connected resistors 15 and 16. When the tracking unit 11 goes into storage, the resistors 15 and 16 are disconnected from the inverting input of amplifier 12, and instead of them, using switch 23, connects resistor 22, which has the same resistance value as resistor 24. Therefore, the storage current of amplifier 12, rather than input current, flows through storage capacitor 13 in storage mode as a result, changes in voltage on the storage capacitor are reduced during the recovery of information & l information and the accuracy of the integrator is improved. In the recording mode, the initial conditions of the integrator works as follows. If after a long stay in the de-energized state of the integrator it is connected to the mains supply, then at the first moment of time the voltage Uj. for the time the driving capacitor 33 is zero and the relay element 34 is set to a state in which its output signal has a single value. In this case, the switch 9 connects the input of the tracking-storage unit 11 with a source of initial conditions (,). At the same time, the output signal of the element IS-HEN 19 of the key 14 is transferred to the closed state regardless of the signal at the output of the allocation unit 18 modules. As a result, the voltage of the initial conditions is recorded in the tracking-storage unit 11, i.e. condition and -U is provided. . Under the action of the difference signals Uy Bbtti, the comparison unit, 17 operates, the allocation unit 18 connects the module using the switch 2 to the output of the comparison unit to the input of pr4 of the voltage generator 3 and the last, working at an increased frequency i, provides a quick code change in the counter 5 to those until the reference unit is turned off, i.e. before. the moment when the difference between. and becomes less than the threshold 01 of the start of the comparison unit. The recording time of the initial conditions in the integrator (t) is determined by the time from the processing by the tracking unit - storing the maximum value of UCD, with a given error. Therefore, the time delay tp formed by the time relay 31 must satisfy the need - both are baked by the appropriate choice of the constant charge time of the driving capacitor 33 and the pickup voltage Ucp of the relay element 34. When during the charging process of the capacitor 33 the voltage across it exceeds the pickup threshold relay element 34, the output signal of the latter takes a zero value and the analog-to-digital integrator switches to the integration mode of the input signal. Let us now consider the work of the integrator in the information recovery mode during short power supply interruptions. When the voltage U in the supply network disappears, the output voltages E, the voltage sources 27, 26, 51 take zero values, and the nature and duration of the transients in the output circuits of these voltage sources may differ significantly from each other (see the timing diagrams in Fig. 2). As long as the voltages E, E-, E are close to the nominal values, the voltage across these transistors, which corresponds to an open state, is supplied from the base of the input transistors 42-44 from the voltage dividers formed by the zener diodes 45-47 and the resistors 48-50. In this case, trajectories 38 and 30, in which an opening voltage U (negative polarity) is applied to the gate of the MOS transistor 2O. As soon as any of the voltages E, E, E comes out of the permissible zone determined by the voltage of the stabilization of the Zener diodes 45-47 (the moment of time in Fig. 2), the output voltage of one of the voltage dividers is sufficient to turn off corresponding to the input transistor, and the latter opens, shunt the base of transistor 38. At the same time, the collector current of transistor 38 decreases, transistor 30 goes out of saturation and due to positive coupling across the resistor 40, the power supply voltage detector 29 switches to another This is the state in which the transistors 38 and the ZO are closed, and the closing voltage arrives at the gate of the MOP transistor 20 (positive polarity). Peak detector 28 maintains the power supply during the power interruption; the positive voltage values on the AC and the gate O-transistor 20 provide the most closed state and small leakage currents. As a result, the storage capacitor 13 is disconnected from the amplifier 12 and the voltage on it (Uj.) Changes over the initial level U o from the initial level U o by a small amount & and {Li, 1 U, where is the voltage on the capacitor 13 at time tj Since the power supply voltage detector 29 ensures that the storage capacitor 13 is disconnected under the condition that it moves out of the permissible zone of at least one supply voltage, the normal conditions of the integrator functional nodes that occur after this do not change the charge on the storage capacitor. During the time;, the discharge of the driving capacitor 33 occurs through the resistor 36 and the relatively small input capacitance of the relay element 34 (the diode 35 when the atom is mixed by the voltage on the capacitor 33 to a non-continuous state). The constant discharge time, ((gDB Cjj is the capacitor capacitance 33, and RJ the resistance of resistor 36) is chosen so that over a period of time the voltage on the capacitor (U.) is not less than the τ threshold of the hysteresis relay element 34 (Ugp). ensures that relay element 34 is installed when U, fli e is restored, in which the output signal is zero, therefore, in the proposed integrator, short power interruptions do not trigger the time switch 31 and the input of the tracking unit 11 to the output of the digital-to-analog converter 8 before opening the MOS transistor 20, which reduces (almost to zero) the integrator error due to the influence of transitions of processes in the recording circuit for initial conditions during short power interruptions. constant discharge time of the capacitor 33, which allows the integrator to tell the property of distinguishing short supply interruptions (with a duration of t-gp) from long, after which it must provide vats initial conditions of the recording mode. The occurrence of voltage in the supply network after its short-term disappearance causes an increase in exhausted voltages E, E, E of sources ranging from 27, 26, 51 from zero to nominal values. In this case, the state of the voltage detector 29, corresponding to the closed ICP transistor 20, is maintained by the open input transistors 42-44 as long as at least one of these voltages is outside the allowable area. As soon as the last of the voltages E, E, E takes the permissible value, at which the supply voltage, close to the nominal (time t. In Fig. 2), is applied to all functional units of the integrator, the corresponding input transistor closes, and ZO under the action of positive feedback through the resistor 4O, the relay is switched to the Indoor state and the opening voltage is applied to the gate of the MOS-arazistor 20, (negative polarity). After the opening of the MOS transistor 2O at the output of the tracking unit-11, is set to the critical voltage, determined by the potential on the capacitor and close to the value of the voltage U Q, which was before the interruption in the power supply, If O: y, then the comparison unit operates 17, and in the integrator, information is restored in the same way as when a counter is failed. After connecting the storage capacitor 13 to the output of the amplifier 12, a potential change in the potential on the capacitor 13 (uU,) is possible, leading to an increase in the integrator error. The reasons for this error are as follows. At time t {see FIG. 2) when the MOS transistor is turned on, the operational amplifier 12 can be in the saturation state and it takes a certain time () to translate it into a linear mode, during which the storage capacitor 13 is recharged by the value of whether it is under action. the maximum output voltage (Up amplifier 12. In addition, after leaving the stage, operational amplifier 12, operation in linear mode, comes to steady-state (,) in the time determined by its frequency properties. During this time, a recharge also occurs condenser 13 (on the value of DI.). Usually, ovs ow, the most significant first component of the error (). In order to reduce these integrator errors, the operational amplifier 12 in the tracking-storage unit 11 is covered by a nonlinear negative by connecting to it a nonlinear element 25 that functions as a two-sided limiting circuit, and a resistor 21 is turned on between the output of amplifier 12 and MOS transistor 20. The non-linear element 25 limits the output voltage of amplifier 12 to JQ, which is determined by the sample voltage corresponding zener diode (52 or 53) and voltage drop across the open diode (54 or 55). With output d 1, the operational amplifier 12: at the time of opening the MOS transistor 20 is in linear mode, which allows reducing the time t and accordingly, the first component of the indicated error (uU) is practically zero. By introducing a resistor 21, the time is increased by recharging the capacitor 13 in a time interval when the amplifier 12 is operated in a linear mode, which reduces the second component of the error (dO). So, the resistance of the resistor 21 is chosen much less than the feedback resistor 16 and the input resistance of the comparison unit 17, then the xamic range of the output voltage of the tracking and tracking unit, and hence its static accuracy, remains practically unchanged. a razistor between the storage capacitor and the resistor 21 connected to the amplifier's extra 12 allows the absolute value of the voltages on these electrodes of the MOS transistor to be limited in all modes of its operation (JoYOjOn defined by the nonlinear element 25; required for controlling the MOSFET, and consequently simplifying its control circuits (by using the operating amplifier’s power supply), as well as reducing the integrator’s error by reducing the effect and a storage capacitor of leakage currents through a closed MOS transistor. Thus, by introducing into the analog-digital integrator an appropriately constructed and switched on power voltage and time relay, as well as a key MOS transistor, a peak detector, two-sided limiting circuit and other elements and connections, a significant reduction in information recovery error is achieved. integrator after short power interruptions. Claim 1. Analog-digital integrator containing two sources of opposite polarity and sequentially connected first switch. The first information input of which is the information input of the integrator, voltage-to-frequency converter, reversible pulse counter, digital-analog converter , the output of which is the integrator output, the second switch, the other one {the formaton input which is the input of the integrator's initial conditions, the tracking-and-storage unit, the unit equal, connected by a different output to the output, ui (a tipo-analog converter, and a selection module of the module, the input of which is connected to the second information input of the first switch, and an output connected to the control input of the first switch, partly to the first input of the NAND element connected by an output to the control input of the storage tracking unit, characterized in that, in order to increase the integrator’s accuracy during short power interruptions, it contains Ikovy detector, voltage signaling device. Neither the time relay whose output is connected to the second input of the NAND element and to the control input of the second switch, the time relay input is connected to the positive polarity voltage source and to the peak detector input whose output is connected to the first auxiliary input of the tracking unit - storage and power supply of the detector, power supply voltage connected high-speed to the second auxiliary input of the tracking unit - stored, two groups of input voltage signalization voltage signaling device generator are connected to two main and groups additional sources of voltage breakdown and negative polarity, 2, Analog-digital integrator according to claim 1, characterized in that in it the supply voltage detector contains an output stage on two transistors of different conductivity type, the output of which is the output of a signaling device, two groups input transistors of different Tima conductivity and two groups of voltage dividers, formed by series-connected Zener diodes and resistors and connected by inputs to the corresponding inputs of the indicator, The outputs of the voltage dividers are connected to the bazak of the corresponding input transistors of different types of conductivity, the emitters of which are connected to the zero potential bus, and the collectors are combined and connected to the input of the output stage, 3, Analog-to-digital integrator according to claim 1 c, chopper-storage contains an operational amplifier, in a circuit between the inverting input and the output of which are included, a two-way limiter AND a serially connected storage capacitor, a MOS transistor connected The first gate and the substrate to the additional inputs of the block, and the first limiting resistor, are connected between the inverting input of the operational amplifier and the input of the block, a serially connected normally closed switch and a second limiting resistor, and between the inverting input of the operational amplifier and the zero potential bus are connected in series the third limiting resistor and a normal but open key, the control input 7 05 of which is connected to the control gate of the normally closed key and to the control input the block, the node connecting the first limiting resistor to the MOS transistor is the output of the block. Sources of information taken into account in the examination 1. US Patent No. 3783399, Inventions overseas higher. 28, 1974, No. 1, 2. USSR author's certificate No. 507872, M.KTif G06 Q 7/18, 1975 (prototype). % / l. -5jC3-H h 55 FIG. / 52 5 FIG. 2