SU813263A1 - Three-phase network electric energy parameter meter - Google Patents

Description

one

The invention relates to information and measurement technology and can be used to measure symmetrical components of voltages or currents of a three-phase network, as well as in the construction of information-measuring systems for monitoring electrical energy quality parameters.

A device for measuring the amplitude-phase asymmetry of a three-phase voltage system, comprising a modulating voltage generator, three identical ring modulators, whose inputs are connected to the phase conductors of the three-phase system and to the modulating voltage generator and indicator 1, is known.

The disadvantages of this device include the presence of two tunable phase-shifting circuits and pre-tuning the device according to the maximum indication of the indicator, while the change in the nature of the asymmetry of the three-phase voltage system causes a detuning of the phase-shifting circuits, i.e. for this. devices are characterized by low accuracy and low speed.

A device for determining orthogonal components of zero-voltage direct and inverse sequences of voltages of a three-phase network is known, which contains multipliers, a quadrature phase splitter, adders, smoothing filters, and a selective filter t2j.

The disadvantages of this device are relatively low speed due to the presence of smoothing and selective filters, and the need to use an additional functional converter to select the voltage moduli of symmetrical components that limits the scope of application of this device.

The closest in technical essence to the proposed three-phase network power quality parameter meter, comprising multipliers, adders, indicators, device memory, switch, frequency multiplier, quad, root-coupler device, voltage-code converter and control unit, voltage converter-voltage-code connected to the first inputs of the first and second multiplication units, the second inputs of which are connected to the 0 first and second inputs of the first storage device, the outputs of the first and second The multipliers of connection P to the first inputs of the first and second adders, the outputs of which are connected to the second storage device, the output of which is connected to the first input of the third multiplication unit, the second input of which is connected to the output of the third storage device, the output of the third multiplication unit is connected to the first input adder, the output of which is connected in series through the quad, the fourth adder and the root cantilee device is connected to the inputs of the first, second and third registered devices Actually, one of the device input buses is connected via a frequency multiplier to the inputs of a voltage-code converter and a control unit, the outputs of which are connected to the corresponding control inputs of all units of the device C3}. The disadvantage of this device lies in its low accuracy due to the effect of non-informative parameters on the measurement results. This is especially true when measuring network and neutral displacements that are determined by reverse and zero sequence voltages, since in real electrical networks the reverse and zero sequence voltages are 10 to 100 times less than the voltage of the direct sequence. The purpose of the invention is to improve the accuracy and expansion of the amplitude range. The goal is achieved by the fact that in the parameter meter, which contains multipliers, adders, indicators, memory devices, a switch, a frequency multiplier, a quadrant, a root-magnet device, a voltage-code converter and a control unit, the output of the converter is connected to a code-code the first inputs of the first and second blocks yivAozheni, which are connected to the first and second outputs of the first memory of the device, the outputs of the first and second multiplication blocks are connected to the first inputs of the first and second blocks cyjB & iaTopOB, the outputs of which are connected to the second storage device, whose input is connected to the first input of the third multiplication unit, whose input is connected to the output of the third storage device, the output of the third multiplication unit is connected to the first input of its third adder, the output of which is connected in series the quad, the fourth adder and the root-removing device are connected to the inputs of the first, second and third recording devices; one of the input buses of the device is connected via a frequency multiplier And with the inputs of the voltage-code converter and the control unit, the outputs of which are connected to the corresponding control inputs of all the units of the device, a key, voltage dividers, a resistor, a series-connected division unit, a function converter, a register and a voltage source are entered, the second and third outputs of which are connected to the first inputs of the fifth, sixth and seventh adders, the second inputs of which through the corresponding voltage dividers are connected to the input buses of the device, the output switch through a switch and a resistor connected to the common bus of the device, and the first, second and third inputs - the outputs of the fifth, sixth and seventh adders control inputs of input units connected to respective output control unit 4i. FIG. 1 is a block diagram of a meter; in fig. 2 - time diagrams of his work. The input buses A, B, C through the dividers 1,2 and 3 of the voltage, the adders 4, 5 and 6 of the analog summation, the switch 7 is connected to the converter 8 the voltage-code. The first inputs of multiplication units 9 and 10 are connected to the outputs of the converter 8, the second inputs to the outputs of the storage device 11, and the outputs through the adders 12 and 13 to the inputs of the storage device 14. The first inputs of the multiplication unit 15 are connected to the outputs of the storage device 14, the second the inputs with the outputs of the storage device 16, and the outputs through the adder 17, quad 18, the adder 19 and the root-extracting device 20 to the recording devices 21, 22 and 23. The outputs of the accumulator 17 through the division unit 24, the functional converter 25 and the register 26 Connected to the first control inputs of the source 27 of the three-phase reference voltage direct sequence, the outputs of which are connected to the second inputs of the adders 4, 5 and 6. Bus A is connected via frequency multiplier 28 to the control inputs of the converter 8, control unit 29 to the second control the input source 27. The input of the inverter 8 through the key 30 and the shunt resistor 31 is connected to a common bus. Consider the operation of the proposed device. The input voltages are id (t), U.g (t) and Uc (t) fl) Hr. 2, a, b, respectively, are fed to the inputs of the switch 7. The voltage id (t) is also fed to the input of the frequency multiplier 28, and pulses are generated at its output (Fig. 2, d), the period of Cator is TX / n, where T is the period of network voltage, p is the coefficient. frequency multiplier (in Fig. 2, conditionally adopted in clause 6). After the signal has arrived, the Start-up to the input of the block 29 begins to generate signals, the timing diagrams of which are shown in FIG. 2, k-n. The operation of unit 29 is synchronized by pulses from the output of frequency multiplier 28 and is rigidly associated with a period T; Id (d) voltages (in Fig. 2, id (1) periods are conventionally shown by thin vertical lines of communication), with the beginning of periods from being read from the moment of arrival of the signal. Start at the input of unit 29. At the first stage of operation of the device, which is 4 the period of the voltage rf (1) (approximately 80 ms), the initial phase of the reference voltage of the source 27 is determined; At the output of the block 29 (Fig. 2, k), a low potential (logical O) closes the key 30. When closed the key 30, the input of the converter 8 is shunted by a resistor 31 whose value is chosen such that the maximum the values of the input voltages did not cause the converter 8 to overflow. In the first period, the signals from the outputs of block 29 are connected to the input of the converter 8, the voltage UA (t), in the second period - the voltage Ug (t}, in the third period - the voltage Uc ( t (Fig. 2, l, m, n, respectively). The input voltage of the converter 8 is shown in Fig. 2, e. At the beginning of each period, a pulse is not formed (Fig. 2, o), which sets the adders 12 and 13 b state zero, at time t. 1 n the pulses from the output of the frequency multiplier 28 (Fig. 2, d) start the converter 8 (the encoded instantaneous values of the voltages are marked by dots in Fig. 2, e). At the same time, output pulses are selected at the output of block 29, and corresponds to the choice of the constants sin - and cos -, which are supplied to the inputs of blocks 9 and 10 multiplication, respectively, on the other inputs of which the output code of the converter 8 is fed. These -codes are multiplied in blocks 9 and 10 and summed up with the contents of adders 12 and 13 At the end of the first exit period x adders 12 and 13 codes are equal to CA (t,) sin ± L,

23G

and E

: h) soz121

At the beginning of the second period, the adders 12 and 13 are set to zero. Then the whole cycle of work 65

Et

arctg sd

 In function converter 25, the code is also calculated.

(3)

H

Claims (1)

2 devices are repeated; at the end of the second period, at the output of adders 12 and 13, the codes are equal to CB S U (t,.) Sin, b, U (t,) cosi. The values of c, cg, ri c can be interpreted as sine, and B d, b as cosine orthogonal components of the first harmonic of the voltages id (e), U {j (t) - and Uj (t) of the three-phase network. At the end of the third period, a pulse is formed, which sets the adder 17 to the zero state. In the fourth period, the value of the initial phase voltage of the direct sequence of a three-phase network is calculated, which is entered into the source 27. In block 29, the control signals are generated, which are used to select the orthogonal component codes sd, c, cc, bg n from memory 14 be, and from the storage device 16 - constants +1/3, -1/6, - 1/6 - and Uztb. These codes are multiplied in multiplication unit 15 and summed up with the contents of adder 17. The output code of adder 17, equal to tG c-b B W l + b + 6 ° (Fig. 2, y), is entered into block 24 dividing. Then the pulse again sets the adder 17 to the zero state. Next, select the codes Bd, bg, be, and the constants +1/6, -1/6, -1/6, + VT / 6 and - TT / 6, which are multiplied and summed with the contents of the adder 17. The code T A -6-TH (FIG. 2, t) is entered in the division unit 24, while the division b is also performed. on s. The quotient of dividing b + on s is fed to the input of functional converter 25, where the code of the initial phase voltage shift angle is calculated for the direct sequence of a three-phase network which is entered in register 26 (fig. 2, x). At this, the first stage of the device operation (the end of the second stage corresponds to the beginning of the fifth period of the voltage id (1). At that, the signal takes the value of logical 1 and the key 30 is expanded. The voltage Uon.A rel. In .c are in the form of a stepped sinusoid. At time t, these voltages are equal to Uon.ft (t, -) Von.sin f (i - S), Ucn.) W- () - fL) Von.sin H () Amounts UA (t) and Uon.) Ue (t) and Uona (t), Uc (t) and Uon.c (t) from the outputs of adders 4, 5 and 6 through the switch 7 are fed to the input of the converter 8. Since they are converted In the code, only instantaneous values of voltages at times t, the step form of the voltage Uon.B op.s influences the results of transformations. Therefore, further, the reference voltages are considered as sinusoidal (Fig. 2, g, s, i), the frequency of which coincides with the network frequency, and the initial phases are equal to „2 (2 2jr 27Г, ЗГ 7ff Uoac (t) Von sin (at - S , f-) The three-phase network voltage U (t), 4 (1) and Uc (t) can be decomposed into direct voltage and zero-sequence voltage of the fundamental frequency and the voltage of higher harmonics. And most of the weight is direct voltage , the value of which is 10-100 times greater than the value of the other components. The beginning of the phase h voltage The consistency is associated with code 5, the EANOSIKSH into register 25 in the form of the relation (3), from which it follows (Vf-.-r, i.e., the system voltage system and the direct sequence of three-phase network voltage are in antiphase, and therefore , their amplitudes are subtracted. In the second stage of the device operation, the key 30 is opened, therefore the conversion gradient of the converter 8 increases and the weight of the low-order unit decreases. In the second stage of the fifth to seventh periods of voltage Ud (t), the sequence of control signals is the same as on the first-third m periods of the first stage (FIG. 2, p), but the DSD, LSR, DDS, Dd, Dbv and db codes are entered into the memory 14 (—the orthogonal components of the difference between the input voltages and the reference voltage system; at the beginning of the eighth period, pulses are generated (FIG. 2, c, c), which set adders 17 and 19 to zero. Then, the codes DSD, ucg, ds, Db, and dbs are selected from memory 14, and from memory 16, the constants +1/3, -1/6 , -1/6, - UT / b and + UT / b, which are multiplied in block 15 and summed up with the contents of the adder 17. The output code of the addendum 17 is equal to hp. + Ull Ds lc v V ( Fig. 2, h) is entered in a quad 18, squared and summed with the contents of the adder 19. Then the adder 17 is again set to zero, and the codes Dd, Db, & h (- About CB and DS (, and from memory 16 are the constants +1/3, -1/6, -1/6, + UZBU and - UzU, which are multiplied and summed with the content of adder 17. The output code of adder 17 equal to L b + D - j d bc - –g L b, + is entered into quad 18, squared and summed with the contents of adder 19. The output code of adder 19 equal to ls + db (fig 2, w) is entered korneizvlekayuschee device 2, where is calculated - / + DRG strand size VQTKA numerically equal to the deviation voltage three-phase networks and zanosits the recording unit 21. A similar sequence of control pulses rails (Fig. 2, cc) allows the voltage unbalance of a three-phase network. calculating algorithm can be described by the formulas A c - - HS mT in T m with s a s b - - -g- l T VHCCHM - carried out. from the output of the root extracting device 20 is entered into the registering device 22,. The algorithm for calculating the displacement of the neural voltages of a three-phase network is described by the formulas - dsd + -j ds + 111 bo yd4d + -jAbB + -jdbct a :. t i “DO CM. Neutral code is entered into the registering device 23. Thus, the meter of the quality parameters of the electric three-phase network allows to increase the accuracy and extend the working range of measurements of the parameters of the quality of the electric energy by 5-10 times. The invention The measuring instrument of parameters of electric energy of a three-phase network, contains multiplying units, adders, indicators, device memory, switch, frequency multiplier, kvarator, redistributing device, voltage-code converter and control unit, output converter code-code is connected to the first inputs of the first and second multiplication blocks, the second the inputs of which are connected to the first and second outputs of the first storage device, the outputs of the first and second multiplication units are connected to the first inputs of the first and second adders, the outputs of which are connected to the second storage device The output of which is connected to the first input of the third multiplication unit, the second input of which is connected to the output of the third storage device, the output of the third multiplication unit is connected to the first input of the third adder, the output of which is connected via series-connected square, fourth adder and core of the nonreferring device of the second and third recording devices, one of the input buses of the device is connected to the inputs of the voltage-code converter and the control unit through a frequency multiplier, ode which are connected to respective control inputs of all the units of the device, characterized in that, in order to increase the accuracy and range of amplitude expansion, it entered key, voltage dividers ,, resistor series-connected dividing unit, a function generator, a register and the source. the reference voltage, the first, second and third outputs of which are connected to the first inputs of the fifth, sixth and seventh adders, the second inputs of which through the appropriate voltage dividers are connected to the input buses of the device, the output of the switch through the switch and the resistor are connected to the common device, and the first, second and third inputs ti - with the outputs of the fifth, sixth and seventh adders, the control inputs of all input units are connected to the corresponding outputs of the control unit. Sources of information taken into account in the examination of 1, Copyright Certificate of the USSR 375592, cl, G 01 R 29/16, 1973, 2, USSR Copyright Certificate 377705, cl. G 01 R 29/16, 1973, 3, USSR Copyright Certificate for Application No. 2607253,