SU811272A1 - Device for solving two-dimensional problems of mathematical physics - Google Patents

Description

adjacent on the row of switching units, corresponding to the inputs of the outermost on the row of blocks of kammutadia Connected to the output of the input block. In addition, the summation block contains a one-digit adder, AND elements, AND element groups, registers, OR element, with the first, second, third, fourth, and fifth inputs of the summation unit connected to the first, second, third, fourth, and fifth inputs of the adder. The output of which is connected to the first inputs of the first and second elements I, the outputs of which are connected to the information inputs of the first and second registers, the first outputs of which are connected to the first inputs of the elements of the first and second groups, the second inputs of which are connected to responsibly with the outputs of the third and fourth elements And, the second outputs of the first and second registers are connected to the first inputs of the fifth and sixth elements AND, the outputs of which are connected to the inputs of the OR element whose output is connected to the output of the summation unit, the outputs of the elements of the first and second groups connected to the group of outputs of the summation unit, the second inputs of the first, second, fifth, and sixth elements And are connected to the third group of control inputs of the inputs of the summation unit, the first and second inputs of the third element And are connected to the first S. Ruppi control their summing unit inputs the first and second inputs of the fourth AND gate connected with the second group of control inputs of summing block.

FIG. 1 given the proposed device; in fig. 2 and 3 are the structures of the summation blocks and the mode setting.

The device contains a control unit /, input unit 2, output unit 3, comparison unit 4, first address register 5, second address register 6, matrix of the JUMAN unit 7, switching blocks 8, mode block 9.

Each summation block contains a five-input single-bit adder 10, a first register 11, a second register 1Z, a first element And 13, a second element And 14, a sixth element And 15, a fourth element And 16, a fifth element And 17, a sixth element And 18, The first group of elements is AND 19, the second group of elements is AND 20, the element OR 21, the first output bus 22, the second output bus 23, the inputs of the two input one (bit adder 24, the control inputs of the summation unit 25-30, the output of the summation unit 31, the first input mode 32, the second input mode 33.

The mode block 9 contains the first trigger 34, the second trigger 35, the inputs of the mode block 55 and 37, the outputs of the mode block 38 and 39.

The device is designed to solve a system of equations of the form

 i-.i + t (+ l. / + Uij-i + / 7 + 1 -

-4i;,; + /, 7 o,

where i 1, 2, ... M / 1, 2, ... M. The device works as follows.

Each summation block 7 corresponds to two adjacent unknowns in a row (Uij, Uij + i) or in a column (Uij, f / i + l-).

In one of the registers //, 12, summation block 7 stores the next approximation of the unknown with the even sum of indices ("even unknown," even register), in the other - the next approximation of the unknown with odd sum of indices ("odd. Unknown," odd register).

If the summation unit 7 stores two adjacent unknowns in a row, its outputs are connected to the inputs of the switching blocks 5 adjacent to the left and right and the inputs of adjacent additions at the top and bottom of the column of the addition units 7. If the summation unit 7 stores two neighboring unknowns by a column, then the outputs they are connected to the ports of the top and bottom adjacent to the switching unit 5 and the inputs to the left and right of the row of the summing units.

Let the rows of the matrix of the summation blocks 7 with odd numbers "odd rows) in the first registers of the summation blocks 7 store" even unknowns ("even registers), in the second registers 12 -" odd unknowns ("odd registers); in the rows of the matrix of blocks of summation on 7 even-numbered numbers — vice versa ("even cTipoKH): the first registers of the 11 blocks of the summed-up AND | 7 are" odd, and the second registers 12

summation blocks - "even.

At the first half-step of each iteration, formula (2) is realized, i.e., new approximations of the even unknowns are computed:

 one

/. () I 7 / (y-1) g // (I-1),

/ (-)

 (Ui-ij -rUi + ij + Uij-i j (2)

(ft-l)

/ l

f //;),

and I

7 + 1

i + j is an even number.

The input block 2 issues in a sequential code, starting with the least significant bit, the values of the boundary conditions for "even

unknowns to the inputs of the external summation blocks 7 in the outermost and odd lines of the switching blocks 8, and the values of the corresponding right-hand parts fa to the inputs of all the summation blocks 7, to other inputs

which receives the serial code from its output, the output of the corresponding switching unit S and from the adjacent summation units 7. At the same time, the control unit / outputs a setup signal to one

Claims (2)

the trigger 34 to the control input 36 of the mode block 9 and the setting signal to zero of the trigger 35 to the control input 37 of the mode block 9. As a result, the mode block 9 outputs the 38 input to the mode input 32 of the summation blocks 7 in the "odd rows of the matrix of the summation blocks" The signal, and the output 39 to the input mode 33 summation blocks - zero signal. Single and zero signals from the outputs 38 and 39 of the mode block 9 are fed to the inputs of the switching unit 8 mode in "odd lines" and provide the output from the switching blocks 8 to the inputs of the summing units 7 information coming from the output of the left-side summing units 7. To the inputs of mode 32 The summation blocks 7 in the even-numbered lines are fed to the output 39 of the mode block 9, and to the inputs of mode 33 a signal is output from the output 38 of the mode 9 block. The inputs of the switching unit 8 in the even-numbered lines are also output from the outputs 38 and 39 of the mode block 9, i.e. inverse Signals with respect to "odd lines" that provide output from switching blocks 8 to the inputs of summation blocks 7, information coming from the output of the right-adjacent summation blocks 7. Such a sequence of control signals ensures that information from the outputs of adders 10 is received into the even-numbered registers and outputs information from "Odd-numbered registers to the outputs of 31 summation blocks 7. After passing (n + 2) cycles of operation of the device in" even-numbered registers, the next approximations to "even unknowns by formula (2) are formed. 8 for the five clock cycles, four (for the Laplace equation) or five (for the Poisson equation) numbers are added and the contents of the registers 11 and 12 of the summation block 7 are shifted. During the two subsequent cycles, the signals from control device 1, feed to inputs 36 and 37 mode 9 blocks, triggers 34 and 35 are set to zero. As a result, mode block 9 outputs, at outputs 58 and 39 to inputs of mode 32 and 33, summation blocks 7, zero signals, which prevents information transfer between summation blocks 7 and by shifting the even-numbered registers, division by four is provided in the formula (2). At the second half-step of each iteration, the formula (3) is realized:; lf -1 (r;, + (/; ,,;; - bi; l, + -f, + fij, where: / + / is an odd number, Uij is the required solution of the problem, Voj, UN + I, /, Uio, Ui, M + - known boundary values of the solution, fij are known values, k is an iteration number. The difference from the first half-step is that, according to the signals of the control unit /, applied to the inputs 36 and 37 of block 9, triggers 34 and 35 are set to the zero and one states, respectively. As a result, the mode block 9 outputs to the "odd and even" even rows of the matrix of the summation blocks 7 inverse to the values on the first the footstep values of the signals to the corresponding inputs of the switching unit 8 and summation blocks 7. This ensures that information is received into the odd registers and outputs information from the even registers to the outputs of the 31 summation blocks 7. Otherwise, the device operates during (n + 2) clocks The second half-step is similar to the work on the first half-step.The control unit 1 sets the addresses of the registers of the summation blocks 7 to the address registers 5 and 5 and when the signals on the elements And 17 or / 8 match, inputs 25, 26 or 27, 28 read the contents forward the register 11 or 12 of summing blocks 7 in the comparator 4, where a comparison is performed decision values ua vreM8NI on two adjacent iterations. Subsequent iterations are performed in a similar manner. When the solutions on two successive iterations differ by a predetermined small value, i.e., the termination criterion of the iterative process is fulfilled, the comparison unit 4 outputs a signal to the control unit /, which produces addresses to the address registers 5 and 6, which select the given registers of summation units 7 for reading solutions from them into output unit 3. Introducing new units and communication with them reduces the amount of equipment required. Claim 1. Device for solving two-dimensional problems of mathematical physics, containing a matrix of summation blocks, the output of each summation block of which is connected to the first inputs of two summation blocks adjacent to a table, the input block whose output is connected to the second inputs of the summation blocks, the output group of each outputs of which are connected to the first inputs of the comparison unit and the output unit, the second inputs of which are connected respectively to the first and second outputs of the control unit, the input of which is connected to the output of the unit with the third output of the control unit is connected to the input of the input unit, the fourth and fifth outputs of the control unit are connected to the inputs The first II second address registers, the outputs of the first address register are connected to the first group of control inputs of each block summed up, the outputs of the second address register are connected to the second group of control inputs of each summation block, characterized in that, to simplify the device, it contains a task block mode and switching units, and the circuit output of the control unit is connected to the input of the mode setting unit, the output of which is connected to the third group of control inputs of each summation unit and control inputs E all switches, switch outputs are connected to respective third inputs of summing blocks, each block summing kodklyuchen output to the fourth input of this summing unit and to the inputs of the adjacent row of blocks switching, the inputs of extreme line switching units connected to the output of the input unit. 2. The device according to claim 1, wherein the summation block contains a one-digit adder, AND elements, AND groups of elements, registers, OR element, the first, second, third, fourth and n The inputs of the summation unit are connected to the first, second, third, fourth and fifth inputs of a one-bit adder, the output of which is connected to the first inputs of the first and second And elements, the outputs of which are connected to the information inputs of the first and second registers, the first outputs of which are connected to the first the inputs of the elements And the first first and second groups, the second inputs of which AND, the second outputs of the first and second registers are respectively connected to the outputs of the third and fourth elements are connected to first inputs The 5th and 4th elements of the AND whose outputs are connected to the inputs of the OR element, whose output is connected to the output of the summation unit, the outputs of the And elements of the first and second groups are connected to the group of outputs of the summation unit, the second inputs of the first, second, fifth and second elements And are connected with the third group of control inputs of the summation block, the first and second inputs of the third element Both are connected to the first group of control inputs of the summation unit, the first and second inputs of the fourth element I are connected to the second group of control inputs of the summation unit. Sources of information taken into account in the examination: 1.Evrenkov E.V. High Performance Homogeneous Computer Systems. -Novosibirsk, “Science, 1966, p. 38-47 2. USSR author's certificate jYo 603997, - cl. G 06 F 15/32, 04/25/78.