SU811226A1 - Dc voltage stabilizer - Google Patents

Description

delay line 6, devices 7 and 8 of comparison, analog memory element 9, gates 10 and 11, polarity signal selectors 12 and 13, amplifiers 14 and 15, expanders 16 and 17.

FIG. 2 shows a constant component of the 18 output voltage of the stabilizer (on the bus 19) with a static mode of operation of the load 3 and in the absence of oscillations of the voltage at the output of the rectifier 2, a dynamic decrease of 20 constant component 18 of the output voltage of the stabilizer, dynamic increase 21 But the component of 18 of the output voltage of the stabilizer, the pulses 22 and 23 of the high frequency, and the opposite increments of 20 and 21 of the polarity of the voltage (non-temporal component of the output voltage of the stabilizer), result uyuschie nanr zheii 24 and 25 after compensation increment pulses 20 and 21, 22 and 23 equal to voltage 18.

The stabilizer works as follows.

In the static mode of operation, the load 3 and in the absence of the output output of the rectifier 2, the voltage on the bus 19 equals the voltage at the output 26 of the analog memory element and the voltage 18. At the outputs 27 and 28 of the devices 7 and 8 there are no comparison signals. Valves 10 and 11 are open. When the load 3 is dynamically operated or when the output voltage of the rectifier 2 oscillates, there will be an increment in the voltage of 20 and 21. The output voltage at the output 26 remains unchanged, since the analog element 9 and it remembers the voltage 18 for a time longer than the maximum duration of the dynamic increments 20 and 21. At output 27, a differential signal appears only when the voltage on bus 19 is less than the voltage at output 26. At output 28, a differential signal appears (opposite to the polarity of the signal at output 27 only when living and the bus 19 is higher than the voltage at the output 26. Each of the selectors 12 and 13 sends signals only to its polarity. The selector 12 passes only the signal generated by the comparison device 7, and the selector 13 only the signal generated by the comparison device 8 (other polarity) The extenders 16 and Form pulses with a duration greater than the duration of the signals at the output of amplifiers 14 and 15. When the signal from output 27 arrives at amplifying element 4 (at its wiring input 29), the latter acts on regulating element 1 so that the voltage bus 19 rises (control element 1 is slightly opened). With the arrival of a signal from the output 28 (of another zeroity) in the amplifying element 4, the next-year effect on the regulating element 1 is such that the voltage on the bus 19 decreases (the regulating element 1 is covered). The signal from exit 27, pass through open. valve 10 and transformed into devices

12, 14 and 16 into a pulse, closes the valve 11. After a delay in line 6, the signal from output 27 goes to the control input 29 of the amplifying element 4. As a result, the voltage on the bus 19 ceases to be

less than the voltage of the output terminal 26. The signal at output 27 is fine, and at the control input 29 of the amplifying element 4, the signal stops only after a time equal to the length of the delay in line 6.

All this time, while the signal is present at control input 29, the voltage on bus 19 is greater than the voltage at output 26, so there is no signal at output 27. Thus, on bus 19, an impulse is formed

22 voltages with an amplitude twice as large as the magnitude of the decrease in voltage in the test for the formation of this pulse (the amplitude of this impulse is determined by the gain of the amplified element 4 n and the value of the decrease in voltage in the place of the formation of the pulse).

As soon as the signal at control input 29 ceases, the voltage on bus 19 reaches the level of neutral, caused by decreasing 20. On bus 27, a signal appears again. And so it continues throughout the entire reduction of 20 voltages. As a result, the decrease in voltage 20 is modulated by high frequency emulsions 22 opposite to the decrease in polarity voltage 20. This frequency is determined by the delay in line 6. All the time, there is a decrease in voltage 20, valve 11 is closed, note that a pulse closing the valve is present at the control input of valve 11 during the entire reduction of voltage 20 (high-frequency pulses 22 merge in extender 16 in

a single continuous pulse, but a duration equal to the duration of the decrease 20), and the valve 10 is open. Valve 11 opens only when voltage reduction 20 is terminated, i.e., when modulation with high-frequency pulses 22 ceases.

The valve 10 is closed when the increase in voltage 21 begins. The increase in voltage 21 is modulated by pulses.

23 of the high following frequency, the opposite of the increase in voltage polarity 21. The operation of this channel is similar to the channel in question. This control of valves 10 and 11 prevents the stabilizer from being self-generated. Thus, the pulses 22 and 23 completely compensate the increments of 20 and 21 for example. The tops of these pulses are symmetrical to voltage 18, repeating the shape of increments of 20 and 21

tension Since the generation of pulses

high frequency only occurs during voltage increments, the level of high-frequency oscillations in the output voltage is insignificant. The high-frequency pulses 22 and 23 of the following are smoothed by the low-frequency transistors of the load 3, as well as the RC filters or diode-capacitor filters of its stages. Therefore, the output voltage of the stabilizer is represented for the cascades of low-frequency load 3 by the resulting voltages 24 and 25 equal to the voltage 18.

Consequently, when opening a transistor of a powerful load cascade, 3 power disturbances are not introduced into its highly sensitive cascades. With a static change in voltage on bus 19 (i.e. when changing voltage for a long time), for example, due to a change in temperature or an additional load connected, the voltage at output 26 varies with time, approaching the voltage on busbar 19 (for example, as element 9 serves as an integrating capacitor).

The proposed voltage stabilizer almost completely compensates the dynamic voltage increments, its dynamic internal resistance is zero, and the stabilization factor is infinity. The possibility of this is proved by the fact that in the proposed stabilizer the dynamic internal resistance can be made negative and the voltage increments can be overcompensated, i.e. at the place where the constant component 18 of the output voltage decreases, the resultant voltage 24 can be increased, and a decrease (the load consumes more current, and the output resultant voltage does not decrease, but rather increases). The degree of compensation of the increments depends on the amplification factor of element 4. With a negative dynamic internal resistance, the stabilizer self-generation does not occur, since the amplitude of the compensating pulses depends on the value of the increments of the output voltage constant component, for which the dynamic internal resistance of the stabilizer is positive. The dynamic internal resistance becomes negative due to the variable component.

The use of the proposed stabilizer is as follows.

Each stage of a low-frequency load, both highly sensitive and powerful, is connected by its pair of supply wires to the output of the stabilizer. Directly at the output of the stabilizer, an RC filter or a diode-capacitor filter is installed on each pair of wires. Such a load inclusion completely eliminates any power supply from one cascade to another and reduces the level of electromagnetic radiation caused by the high-frequency component of the output voltage of the stabilizer (filters smooth the high-frequency component directly at the stabilizer).

Other uses of the proposed stabilizer are possible.

The stabilizer will be widely used in precision instrument making.

Claims (2)

1. Belopolsky I.I. P1sources of power for radio devices. M., “Energie, 1971, p. 235-239. 2. Karpov V. I. Semiconductor voltage and current stabilizers. M., “Energie, 1967, p. 41, rps. 23, 24. P , 20 Uj 21