SU809294A1 - Information receiving and transmitting apparatus - Google Patents

Description

one

The invention relates to devices for receiving and transmitting information and can be used in automated traffic control systems for identifying moving objects, such as priority vehicles.

A device for receiving and transmitting information from a control point is known, comprising a high-frequency generator, one output of which is connected to a filter unit connected between a frame antenna laid under a road surface, and a receiver connected to corresponding gates element inputs, the other inputs of which are connected respectively, to the output of the first IS element and to the output of the clock pulse generator, one input of which is connected to one of the outputs of the frequency divider unit, the input of the connected to another output of the high-frequency generator and the other to one of the inputs of the second element NAND, the output of which is connected to one of the trigger inputs, the output connected to the second input of the second element NAND, and the other input to one of the outputs of the checker reliability, connected to one of the inputs of the second trigger, another input, which is connected to the output of the second NAND element, another output of the validation block is connected to one input of the decoding unit and to one input of the AND element, the other input of the associated c. data processing block, 9 third input - with the output of the first NAND element, one input of which is connected to the output of the second trigger, and the other inputs are connected to the outputs of the shift register, one input of which is connected to the output of the element

S And connected with another input of the second trigger, and other inputs connected to the outputs of the gating element, the output of the shift register connected to the corresponding inputs of the first and

the second I-NB elements and the decoding block associated; During the data processing, one of the gates element outputs is connected to the input of the validation block, and its other output is connected to one of the inputs of the third trigger, the other input is connected to the other output of the clock generator, and the output is connected to one of the inputs of the signal generator GENERAL RESET, others

the inputs of which are connected to the outputs of the receiver, and the output is connected to the corresponding V1.odami clock clock pulses, frequency divider unit, power testing unit and the first trigger 1.1.

The disadvantage of such a device is the possibility of distortion of information at the reception. This is due to the fact that when the first code parcel arrives at the input of the gating element during the presence of a clock pulse on its other input, a false gating of the code sprinkling is possible until the moment of generating the GENERAL RESET signal, i.e. before setting the hard sync mode. False gating is caused by various delays for the purpose of generating a GENERAL RESET signal and in the gating element circuit. Thus, if the delay of the GENERAL RESET signal is greater than the delay of the signal prohibiting its formation, the device will go into hard synchronization mode, which leads to distortion of information upon reception.

In addition, it is possible that the BANNER signal is falsely generated when receiving information from two vehicles during a read cycle, the duration of which is determined from the output of the data processing unit, if, when writing to the shift register, information from the second vehicle complements the previously recorded information to code combination 1111. Obviously that further information will not be received, since the BAN signal is sent to the input of the gating element, which cannot be removed due to the absence of the TRIP signal from the output of the first three ger.

All these shortcomings ultimately reduce the reliability of the acceptance. mama information.

The closest in technical essence to the present invention is a device for receiving and transmitting information from the control point, comprising a high frequency generator, the first output of which is connected to the receiver through a filter unit connected to the antenna, and the second output to the first input of the frequency divider unit , the receiver outputs are connected to the corresponding first inputs of the signal generator GENERAL RESET and the gate element, the outputs of which are connected to the first inputs of the shift register and the validation block, sec The second input of the shift register is connected to the output of the first pulse generator, and the outputs of the shift register are connected to the corresponding third inputs of the first and second AND-NOT elements and the corresponding second inputs of the decoding unit, the outputs connected to the first inputs of the data processing unit, triggers, the output of the first which is connected to the second input of the signal conditioner GENERAL RESET, the output of which is connected to the second input of the frequency divider unit and to the second input of the plausibility checker, the second output of which is soy Inonii to a fourth input of the first pulse shaper and the first inputs of the decoding unit, and the input of the second flip-flop connected to the output of the second AND-NO element, one input of which is connected to the first input of the frequency divider unit, and the other input connected to the output

5 of the second trigger, the second input of which is connected to the output of the imaging unit, and the third input is connected to the output of the first NAND element, one of the inputs connected to the first output of the validation unit, the inverse output of the second trigger is connected to the second input of the first pulse conditioner, and the third input signal conditioner GENERAL

5 RESET and with the third input of the gate element, the second input of the gate element is connected to the second output of the frequency divider unit, the first output of which is connected to the R input of the first trigger, counting

the input of which is connected to the output of the signal conditioner GENERAL RESET 21.

The main disadvantage of the known device is the lack of information about the speed of the priority vehicle, which prevents the data processing device from flexibly controlling the road controller and results in a delay of other vehicles following directions that conflict with the direction of movement of the priority vehicle.

In addition, the device displaces the information about the priority of the first rank by signaling information from vehicles having the priority of the second rank, in the event that

information happens during

read cycle, the duration of which is determined by the data processing unit, and the road controller is controlled only

through a data processing device (for vehicles having a first and second rank preference). The presence of this drawback is due to the fact that in a known device the signal blocking the gating element by one of the inputs is removed on the falling edge of the pulse. REQUEST FOR SPECIAL PASSAGE.

These disadvantages ultimately narrow the functionality of the known device. The purpose of the invention is to expand the functionality of the device. The goal is achieved by the fact that a time interval former, a RESET signal conditioner and a time detection unit are entered into the device, the receiver outputs are connected to the first inputs of the time interval generator, the second input of which is connected to the output of the first, the second output of the frequency divider unit is connected to the third input the time generator and to the first input of the RESET signal generator, the first output of which is connected to the first input, the time determining unit, with the third input of the first generator with the third inputs of the decoding unit and with the second input of the third NAND element, whose output is connected to the second / key input, the first output of the time interval generator is connected to the second input of the time determining unit, the first output of which is connected to the second input of the data processing unit, and the second output — with the second input of the RESET signal conditioner, the second output of which is connected to the third D: 4th unit of the time detection unit and to the fourth input of the time intervalformer, the second output of which is connected to the third in the signal generator RESET, the second output of the data processing unit is connected to the fourth input of the RESET signal generator, the second output of the validation unit is connected to the fourth inputs of the time determining unit and the first generator, the inverse output of the second trigger is connected to the fifth input of the RESET signal, the output of the second shaper is connected to the sixth input of the shaper of the RESET signals. FIG. 1 shows the functional scheme of the device; in fig. 2 and 3 are time diagrams for his work. The device contains a high-frequency generator 1, a filter block 2, an antenna 3, a receiver 4, a gating element 5, a time interval generator 6, a generator 7 of a GENERAL RESET signal 8, a frequency divider block 8, a reliability checker 9, a first trigger 10, register 11 the first driver 12, the first element 13 AND-NOT, the second element 14 AND-NOT decoding unit 15, the data processing unit 16, the second trigger 17, the second driver 18, the element 19 galvanic isolation, 20 forming the RESET signal, the unit 21 definitions of time, third element 22 AND-NOT and cl Here 23. The device operates in two modes: 1. The control of the traffic light directly through the road controller (for vehicles having priority of the first rank) and control of the traffic light through the data processing device (for vehicles having priority of the second rank); 2. Traffic light control only through a data processing device (for vehicles that have priority of the first and second rank). The mode of operation of the device is determined by the key position. In the proposed example, the device is set to the first mode of operation. The operation of the device is considered in the following sequence: receiving and transmitting information from the control point device; measuring the speed of a vehicle equipped with a device for receiving and transmitting information. The reception and transmission of information from the control device is as follows. The high frequency generator 1 continuously sends a REQUEST signal, which, through filter block 2, provides the separation between the information signal from the vehicle and the REQUEST signal and enters antenna 3, where the local area of coverage is. When a vehicle enters the zone of operation of the antenna 3, the information characterizing the vehicle is read in the most effective area of the antenna 3, which is determined by the energy ratios in the inductive connection mode, the geometric dimensions of the antenna 3 and the speed of the vehicle. The informational frequency-controlled signal transmitted from the vehicle is induced in antenna 3, selected by filter unit 2 and amplified by receiver 4, from which output parcels 1 and O are fed to the corresponding inputs of gating element 5 of generator 7 of GENERAL RESET. Shaper 7 of the GENERAL RESET signal on the leading edge of the first code parcel, which is the control bit and synchronized with the information block signal, generates the GENERAL RESET signal, which sets the frequency divider unit 8 and the validation unit 9 to the initial state, and the trigger 10 is set to 1 on the falling edge, wherein the block 8 of the frequency dividers is set to the hard synchronization mode. The trigger 10 is set to the initial state by the input R (n + 1) by the clock pulse from the output of the 8 frequency divider block.

where n is the number of bits in the code combination.

Thus, the trigger 10 at the signal front of the GENERAL RESET generates a signal at the inverse output that closes the driver 7 and the driver 6 of the vehicle’s time interval, thereby generating the GENERAL RESET signal from the first code message and eliminating the possibility of generating false signals GENERAL CROSS from subsequent code parcels

The signals from the second output of the high-frequency generator 1 are fed to the input of a block of 8 frequency dividers, which has two division stages. The first division stage ensures the formation of clock pulses that arrive at the third input of the gating element 5 and gates the parcels 1 and O in their most effective area j (cM. Fig. 2). The maximum O {Dibka in hard synchronization mode is determined the period following the signals from high frequency generator 1.

The gating element 5 generates the sequence 1 and O and detects from the general sequence of code pulses the corresponding elements of code 1. The general sequence of code pulses corresponding to the elements of code 1 and O from the output of the gating element 5 is fed to the clock input of the shift register 11 and to the input block 9 and validation.

The sequence of pulses corresponding to elements of code 1 from another output of gating element 5 is fed to the information input of shift register 11 and written into it, as well as to another input of validation unit 9, which performs / checks received information by Parity and Number of Characters in code combination.

The information is correctly received, signal 1 appears at one of the outputs of block 9 of validation, preparing 01dia corresponding to the inputs of decoding unit 15 and 4 and converter 12, generating the REGISTER RESET signal, the other input of the driver 12 is prepared with a signal from the inverse output of trigger 17 .

The information recorded in the shift register 11 is set in parallel code on the other inputs of the decoding unit 15 and read into the data processing unit 16 by the signal READING, which is processed by the data processing unit 16, which decides on the priority passage of priority vehicles through the intersection (priority of rank

The shift register 11 is reset by the REGISTER RESET signal from the output of the driver 12, which is formed on the falling edge of the READ signal and when the device power is turned on. The need to reset the shift register is primarily due to the fact that it is possible to repeatedly read the same information, while false data about passing through the intersection of the priority vehicle would be recorded in data processing unit 16.

When polling a vehicle having a priority of the first rank, to which a certain code is assigned, for example 1111, information about it is recorded in the shift register 11 from whose outputs is set in parallel code at the n inputs of elements 13 and 14 AND-NOT. After analyzing the received information, the plausibility checker 9 generates a signal TRUE that, through element 13, IS-NOT is recorded into trigger 17 at input S. The trigger 17 is set to its initial state by a signal from the output of driver 18, which generates a RESET signal when the device turns on.

Thus, the element 13 AND-NOT and the trigger 17 reveals information about the vehicles to which priority of the first rank is assigned.

The signal from the inverted trigger output 17 blocks, one of the inputs, the gating element 5, the shaper 7 of the GENERAL RESET signal, the shaper 12 and the shaper 20 of the RESET signal until the completion of the signal formation. REQUEST FOR PRIORITY PASSES, which is formed by the block of 8 frequency dividers, element 14 AND -NON and trigger 17, the signal from the direct output of which prepares element 14 AND-NOT for (n + 1) input and element 22 AND-NOT for the first input. In this case, the AND-14 element 14 remains to be closed by the m (n + 2) input for the time C from the moment the block 8 of the frequency dividers goes into hard synchronization mode. After the time T has elapsed, a sequence of pulses of duration f / 2 and pulse frequency f is formed at the other output of block 8 of frequency dividers. The first pulse of the generated pulse sequence opens element 14 NAND, whose output signal with its trailing edge sets trigger 17 on input T to state O, and the signal from direct output trigger 17 closes element 14 AND NAND.

Claims (2)

1. Certificate of authorship on application 2417187 / 18-24, cl. G08 C 17/00, 1976. 2. USSR author's certificate on application 2544067 / 18-24, cl. G 08 C 19/28, 1977 (prototype).