SU789787A1 - Apparatus for measuring value of random-signal voltage - Google Patents

Description

Trigger mode is connected to the inputs of the prohibition element and the driver, the control inputs of the control unit, the recording trigger, the second input of the reversible counter, the control input of which is connected to the second output of the control unit, the third and fourth outputs of which are connected to the control inputs of the random access memory, the output which is connected to the input of the control unit, the fifth output of which is connected to the second input of the element I, and the outputs of the prohibition element and the former are connected to the inputs of the switch and the second input ohm result counter. The drawing shows an electrical circuit diagram of the device. The device contains a logarithmic amplifier 1, amplitude detector 2, analog-to-digital converter 3, switch 4, reversible counter 5, random access memory b, recording trigger 7, element 8 I, counter 9 of the result, block 10 of indication, counter 11 of the number of counts, trigger 12 of the mode, prohibition element 13, driver 14, control block 15 and decoder 16. The device operates as follows. The measured signal is fed to the input of a logarithmic amplifier 1, compressing its dynamic range. The signal from the output of the logarithmic amplifier, through the amplitude detector 2, is fed to the input of the analog-digital converter 3, which produces a binary code of the number N j proportional to the maximum value of the measured input voltage in the i-th reference point, expressed in decibels. The sampling frequency of the analog signal in the analog-to-digital converter is determined by the frequency of the pulses o, pp arriving at its input from block 15. At the beginning of the measurement cycle, the counter 11, the reversible counter 5, the trigger .12 and the trigger 7 are set to zero. and in the cells of the operative memorized device b, zeros are written. The signal from the output of the trigger 12 determines the recording mode, while the first polling pulse from the output of block 15 goes through the element 13 to the overwriting input of the switch 4 and rewrites the code N from the outputs of the analog-digital converter 3 to the reversible counter 5, the state of which determines the address of the selected cell of the operative storage device 6, at the output of which appears the potential zero recorded in the cell, which arrives at the control input of unit 15. Block 15 generates signals to write a unit to cell A j, which arrive at the information The first and the clock inputs of the on-line backup device 6. The summation of squares of voltages is implemented in the random access memory b as follows: The i-th polling pulse from the output of block 15 enters the rewriting input of switch 4 through prohibition element 13, rewrites the NJ number code from the outputs of the analog-digital converter 3 to the reversible counter 5, while in the cell AJJ. if zero was previously written, then one is written to it. If in a cell of random access memory used at Afj. unit was recorded, then unit potential appears at its output, and block 15 first generates write zero signals into this cell, and then an address impulse pulse, which enters the counting output of the reversing counter 5 and sets it to the N4 + 1 state. , if in the cell N .; + 1 was written to zero, then the unit is written to it, if the unit is written to the unit, zero is written to it, and the reversible counter 5 is set to the state N- + 2 (transferring the unit to the highest bit), and so on. Thus, in the operative storage device 6, a bitwise addition of binary numbers is implemented. Counter 11 counts the polling pulses and, at the end of the n 2 pulses, generates a signal that sets the trigger 12 into the unit state corresponding to the read mode. The signal from the output of the trigger 12 prohibits the passage of the polling pulses through the element 13 to the input of the switch 4, switches the reversible counter 5 to the subtraction mode, removes the signal set to the zero state from the input of the trigger 7, In addition, on the front of the signal from the output of the trigger 12 the driver 14 produces write pulse, set counter 9 to state k, and code of constant number M, which is written to reversing counter 5, generated by switch 4. Number No. is chosen to be greater than or equal to the maximum address of the RAM cell in toruyu may be recorded in the summation unit. When the signal from the output of the trigger 12 arrives, the unit 15 begins to generate address count pulses and zero write signals to the operational memory of device b, while the cells A, A, are sequentially polled and nullified. . When installing the reversing counter 5 to the address of the Ag unit of the senior

the sum of the sum of the signal from the output of the random access memory b sets the trigger 7 to one state, while the signal from the output of the trigger 7 permits the arrival of counting pulses of the result from the output of block 15 through element 8 AND to the counting input of the counter 9.

When the reversible counter reaches the address-ApCj), the decoder generates a reset pulse, setting the counter 11 to the zero state and trigger 12. The output signal from the trigger 12 transfers the device to the write mode, the trigger is set to the zero state and the pulses arrive at the counter 9 prekrgitsaetsa. With the transition to the recording mode, a new measurement cycle begins, similar to that described above.

The frequency of the result count pulses is three times the frequency of the address count pulses.

The code recorded in the counter 9 enters block 10, in which the rms value of the measured random signal is displayed.

Thus, the device makes it possible to increase the measurement accuracy of the rms voltage value, while the measurement accuracy does not depend on the type of distribution of the levels of random signals.

Claims (2)

1. The UK patent number 1364909, cl. G 01 R 19/00, 1978. 2. USSR author's certificate number 402813, cl. G 01 R 19/02, 1972 (prototype). AND