SU773728A1 - Matrix storage - Google Patents

Description

one

The invention relates to computing and can be used in the development of storage devices on bipolar transistor structures.

A known storage of permanent storage devices, assembled on bipolar transistors, in which information is recorded by applying electrical signals to 10 corresponding external terminals l.

The disadvantage of the accumulator, where the storage elements are included in the collector circuit of the transistor, is not a high enough information density.

The closest in technical essence to the present invention is a drive comprising numerical buses, bit buses connected 20 to numeric buses by means of diodes and memory elements, transistors whose emitters are connected to bit buses and collectors to output buses 1 and, and bases through 25 resistors are connected to the input buses of the storage {2.

The disadvantage of such a storage device is a large number of external leads, which requires a large number of 30

equipment, and this, in turn, leads to an increase in the cost of the entire ROM, an increase in power consumption and a decrease in speed.

The purpose of the invention is to simplify the device.

This goal is achieved in a matrix drive containing serially connected memorizing elements and diodes that are connected between numerical and discharge buses, transistors whose collectors are connected to output buses, emitters - to discharge buses, and bases - through resistors to input buses . groups of transistors and first and second address buses are introduced, the collectors of the first group of transistors are connected to the number lines, the bases are connected to the first address lines, and the emitters are connected to the collectors of the second group of transistors, and the bases of the second transistors are connected to the second ones address buses, and emitters - to a common bus accumulator.

The drawing shows an electrical circuit of a matrix drive.

The device contains numeric bus 1 and bit bus 2, interconnected by diodes, 3, and memory elements 4, the emitters of transistors 5 are connected to the bus bar, and collectors are connected to output buses b, and the bases are connected to resistors 7. Others the leads of the resistors 7 are connected to the input buses 8, the collectors of the transistors 9 of the first group are connected to the number buses 1, the first address buses 10, and the emitters are connected to the collectors of the second transistors 11 and through the resistors 12 to the bus 13, the bases of the transistors are connected to the second adres GOVERNMENTAL rails 14 .. and emitters - the common bus 15.

Matrix drive works as follows.

In the recording mode on the bus 15 serves a zero potential, and on the bus 13 a positive potential, for example 2-5 V, on one of the buses 10 and 14 serves the sampling currents. As a result, the transistors 9 and 11 connected to the selected buses are opened, and one of the number lines 1 is connected to the common bus 15.

The remaining buses 1 remain disconnected from the common bus 15, since in the chain of transistors 9, 11 of these buses at least one turns out to be closed.

On one of the tires 8 serves the recording potential, and the rest - zero potential. At the same time, transistors 5 connected to the selected numeric bus 1 are switched to saturation mode, and the rest are in cut-off mode. According to the recorded information, a write current or zero potential is applied to the output buses, in the first case the write current through the selected transistor being in saturation mode, it goes to the corresponding bit bus, and from there through the diode and storage element to the selected word line, it records. In the second case, the current flowing through the selected resistor 7 flows through the collector junction of the transistor to the output bus and recording does not occur.

In the read mode, as well as during recording, the selected numerical bus 1 is connected, and the rest are disconnected from the common bus 15. A high level potential is applied to the selected input bus 8, and an zero potential is applied to the remaining input bus. At the same time, depending on the state of conduction of the combining elements located at the intersection of the selected, numerical and discharge buses, the current of the selected re- torors 7 through the emitter transitions of the transistors 5, the discharge buses and conductive - 3 memory elements;

flows down to the selected numerical bus or, if the storage elements are not conducted, it goes through the collector transitions to the output buses of the storage device. In the first case, the potential is low on the weekends, the tires, and in the second, the high.

In comparison with the known, the proposed drive provides significant. winnings in the number of external

CONCLUSIONS; Minimum possible

the number of external inferences, the known accumulator is equal to r ,, J-W where N is the amount of information. In the proposed drive, the minimum possible number of external pins is nij. . For example, for a volume of 4096 bits, m 48 and m 26, and in the first case the diode array is too unbalanced (16 numeric and 256 bit buses), which leads to a loss in information density and speed, while in the proposed one. the drive, the number of number and bit tires is 64. If

gn drive, number of bits AND;

numerical tires to equalize, the drive will already have 80 external leads, which leads to the need to connect additional equipment and complicate the drive.

Claims (2)

1. USSR author's certificate No. 506060, cl. G II 11/34, 1973, 2. USSR author's certificate in accordance with application 2697090, cl. G 11 C 11/34 45 18,12.78 (prototype). / r -0S eight d