SU771722A1

SU771722A1 - Associative storage

Info

Publication number: SU771722A1
Application number: SU792704250A
Authority: SU
Inventors: Виктор Фитисович Соломатин
Original assignee: Северо-Западный политехнический институт
Priority date: 1979-01-02
Filing date: 1979-01-02
Publication date: 1980-10-15

Description

Изобретение относится к области запоминающих устройств.The invention relates to the field of storage devices.

Известно ассоциативное запоминающее устройство, содержащее регистр признака опроса, регистр текущего признака, накопитель, схему равенства признаков и ряд логических элементов (1).Known associative storage device containing a register of the sign of the survey, the register of the current sign, drive, circuit equality of signs and a number of logical elements (1).

Недостатками этого устройства являются высокая чувствительность по отношению к влиянию локальных дефектов носителя, сложность конструкции и потеря емкости вследствие необходимости записывать коды-признаки.The disadvantages of this device are high sensitivity with respect to the influence of local media defects, design complexity and loss of capacitance due to the need to record feature codes.

Наиболее близким техническим ре- 1 шением К данному изобретению является ассоциативное запоминающее устройство, содержащее регистр опроса, преобразователь кодов, умножители, сумматор, накопитель, входной и выходной регистры, пороговые элементы [2),The closest technical solution to this invention is an associative storage device containing a polling register, code converter, multipliers, adder, storage device, input and output registers, threshold elements [2),

Недостатком этого устройства является сложность конструкции: оно содержит большое числозапоминающих элементов, сумматоров, умножителей , между которыми установлено большое число связей.The disadvantage of this device is the design complexity: it contains a large number of memory elements, adders, multipliers, between which a large number of connections are established.

Целью изобретения является упрощение устройства.The aim of the invention is to simplify the device.

Цель достигается тем, что в ассоциативное запоминающее устройство, содержащее регистр признака, выходы которого подключены к информационным входам преобразователя кодов, входной регистр, первую и вторую группы умножителей, сумматор, накопитель, информационные выходы которого соединены с первыми входами умножителей второй группы, выходной регистр, входы которого подключены к выходам пороговых элементов, введены дополнительный умножитель, генератор псевдослучайных сигналов и интеграторы, причем выходы входного регистра подключены к первым входам умножителей первой группы, выходы которых соединены со входами сумматора, выход которого подключен к одному из входов дополнительного умножителя, другой вход которого соединен с выходом преобразователя кодов, а выход - со входом записи накопителя, выходы умножителей второй группы подключены ко входам интеграторов, выходы которых соединены со входами пороговых элементов, вторые входы умножителей групп подключены к выходам генератора псевдослучайных сигналов, а вход синхронизации пре3 ^71722 образователя кодов и вход генератора псевдослучайных сигналов соединены с выходом синхронизации накопителя.The goal is achieved in that in an associative storage device containing a feature register, the outputs of which are connected to the information inputs of the code converter, an input register, the first and second groups of multipliers, an adder, a drive, the information outputs of which are connected to the first inputs of the multipliers of the second group, the output register, the inputs of which are connected to the outputs of the threshold elements, an additional multiplier, a pseudo-random signal generator, and integrators are introduced, and the outputs of the input register are connected to the first inputs of the multipliers of the first group, the outputs of which are connected to the inputs of the adder, the output of which is connected to one of the inputs of the additional multiplier, the other input of which is connected to the output of the code converter, and the output to the input of the drive recording, the outputs of the multipliers of the second group are connected to the inputs of integrators, outputs which are connected to the inputs of the threshold elements, the second inputs of the group multipliers are connected to the outputs of the pseudo-random signal generator, and the synchronization input pre3 ^ 71722 of the code generator and the generator input a pseudo-random signals are connected to the output drive synchronization.

На чертеже изображена блок-схема предложенного устройства.The drawing shows a block diagram of the proposed device.

Устройство содержит регистр признака 1, преобразователь кодов 2, дополнительный умножитель 3, входной регистр 4, первую группу умножителей 5₁- 5₄ , сумматор 6, накопитель 7, в состав которого входит'головка записи 8, головка воспроизведения 9 и усилитель воспроизведения 10. Устройство также содержит вторую группу умножителей 11^- 11^ интеграторы 12, пороговые элементы 13, выходной регистратор 14, генератор псевдослучайных сигналов 15. В состав накопителя также входит головка воспроизведения синхроимпульсов 16, усилитель синхроимпульсов 17, подвижный носитель информации 18, усилитель записи 19.The device contains a sign register 1, a code converter 2, an additional multiplier 3, an input register 4, a first group of multipliers 5 ₁ - 5 ₄ , an adder 6, a drive 7, which includes a recording head 8, a playback head 9, and a playback amplifier 10. The device also contains a second group of multipliers 11 ^ - 11 ^ integrators 12, threshold elements 13, an output registrar 14, a pseudo-random signal generator 15. The drive also includes a sync reproduction head 16, a clock amplifier 17, movable rer information 18, recording amplifier 19.

Выходы регистра 4 подключены к первым входам умножителей 5₄ - 5_Д, выходы которых соединены со входами сумматора 6, выход которого подключен к одному из входов умножителя 3, другой вход которого соединен с выходом преобразователя кодов 2, а выход - со входом записи накопителя 7, информационные выходы которого соединены с первыми входами умножителей 11₄- 11_д.Выходы умножителейThe outputs of the register 4 are connected to the first inputs of the multipliers 5 ₄ - 5 _D , the outputs of which are connected to the inputs of the adder 6, the output of which is connected to one of the inputs of the multiplier 3, the other input of which is connected to the output of the code converter 2, and the output to the input of the drive 7 , the information outputs of which are connected to the first inputs of the multipliers 11 ₄ - 11 _{d. The} outputs of the multipliers

11-1 - 11^подключены ко входам интеграторов 12,выходы которых соединены со входами пороговых элементов 13. Вторые входы умножителей 5₄ - 5₄и 11-.- 11₄подключены к выходам генератора 15. .Вход синхронизации преобразователя кодов 2 и вход генератора 15 соедине.ны с выходом синхронизации накопителя 7.11-1 - 11 ^ are connected to the inputs of integrators 12, the outputs of which are connected to the inputs of the threshold elements 13. The second inputs of the multipliers 5 ₄ - 5 ₄ and 11 -.- 11 _{4 are} connected to the outputs of the generator 15.. Synchronization input of code converter 2 and the input generator 15 are connected to the output of the synchronization drive 7.

Устройство работает следующим образом.The device operates as follows.

При записи на регистр признака 1 подается код-признак, а на регистр 4 - информационный код. Устройство управления (на чертеже не показано) запускает движение носителя информации 18. Синхроимпульсы поступают с головки воспроизведения синхроимпульсов 16 через усилитель синхроимпульсов 17 на входы синхронизации преобразователя кодов.2 и генератора псевдослучайных сигналов 15 и управляют их работой. Псевдослучайные сигналы, формируемые на выходах генератора 15, в умножителях 5₄ - 5_Думножаются на постоянные сигналы, поступающие с выходов регистра 4 и представляющие значения отдельных разрядов информационного кода. Выходные сигналы умножителей 5₄ - 5дпоступают на входы сумматора 6. Сигнал с выхода сумматора 6 поступает на умножитель 3 и умножается на псевдослучайный сигнал' формируемый на выходе преобразователя 2. Результат перемножения через усилитель 19 поступает на головку записи 8 и записывается на носителе 18.When writing to the register of characteristic 1, a code-sign is supplied, and to register 4 - an information code. The control device (not shown) starts the movement of the information carrier 18. The clock pulses arrive from the playback head of the clock 16 through the clock amplifier 17 to the synchronization inputs of the code converter 2 and the pseudorandom signal generator 15 and control their operation. The pseudo-random signals generated at the outputs of the generator 15 in the multipliers 5 ₄ - 5 _D are multiplied by the constant signals coming from the outputs of the register 4 and representing the values of the individual bits of the information code. The output signals of the multipliers 5 ₄ - 5 are fed to the inputs of the adder 6. The signal from the output of the adder 6 is fed to the multiplier 3 and is multiplied by a pseudo-random signal 'generated at the output of the converter 2. The result of multiplication through the amplifier 19 is supplied to the recording head 8 and recorded on the carrier 18.

При считывании сигнал с головки воспроизведения 9 через усилитель 10 поступает На первые входы умножителей .11^.- 11₄ ^на вторые входы которых поступают сигналы с выходов генератора псевдослучайных сигналов 15. Генератор 15 синхронизируется импульсами, поступающими с головки воспроизведения синхроимпульсов 16 через усйЛйтель 17. Сйгйалы с выходов умножителей 11₄- 11₄ Интегрируются интеграторами 12. Выходные сигналы интеграторов 12 подвергаются преобразованию в пороговых элементах 13 и результат в форме кода поступает в выходной регистр 14.When reading the signal from the playback head 9 through the amplifier 10, it arrives at the first inputs of the multipliers .11 ^ .- 11 ₄ ^the second inputs of which receive signals from the outputs of the pseudo-random signal generator 15. The generator 15 is synchronized by pulses from the playback head of the clock 16 through the amplifier 17. Signals from the outputs of the multipliers 11 ₄ - 11 ₄ Integrated by integrators 12. The output signals of integrators 12 are converted in threshold elements 13 and the result in the form of a code is sent to the output register 14.

Положительным эффектом описанного устройства является упрощение конструкции - резко сокращается число связей, число умножителей и сумматоров , дискретный носитель информации заменяется сплошным, подвижным, что приводит и к значительному снижению стоимости устройства.A positive effect of the described device is the simplification of the design - the number of connections, the number of multipliers and adders is sharply reduced, the discrete storage medium is replaced by a solid, mobile, which also leads to a significant reduction in the cost of the device.

Claims

(54) ASSOCIATIVE STORAGE DEVICE The invention relates to the field of storage devices. A known associative memory device contains a register of a poll sign, a register of a current sign, a drive, a sign equality circuit and a set of logical elements {ll. The disadvantages of this device are high sensitivity with respect to the influence of local carrier defects, design complexity and capacity loss due to the need to write feature codes. The closest technical solution to this invention is with an associative memory device, containing the poll register, code converter, multipliers, adder, accumulator, input and output registers, threshold elements. The disadvantage of this device is the complexity of the design: it contains a large number of memory elements, adders, multipliers, between which a large number of connections were established. The aim of the invention is to simplify the device. The goal is achieved by the fact that in an associative memory device, containing a register of a sign, the outputs of which are connected to the information inputs of the code converter, the input register, the first and second groups of multipliers, the adder, the drive, the information outputs of which are connected to the first inputs of the second group multipliers, the output a register whose inputs are connected to the outputs of threshold elements, an additional multiplier, a pseudo-random signal generator, and integrators are introduced, with the outputs of the input register being connected s to the first inputs of the multipliers of the first group, the outputs of which are connected to the inputs of the adder, the output of which is connected to one of the additional multiplier inputs, the other input of which is connected to the code converter input, and the output to the recording input of the accumulator, the outputs of the second group are connected to the inputs of the integrators The outputs of which are connected to the inputs of the threshold elements, the second inputs of the group multipliers are connected to the outputs of the pseudo-random signal generator, and the synchronization input of the code converter and the generator input torus pseudorandom signals connected to the output of the synchronization drive. The drawing shows a block diagram of the proposed device. The device contains a register. Character 1, the converter code 2, additional multiplier 3, input register 4, the first group of multipliers 5, the adder 6, the drive 7, which includes the recording head 8, the playback head 9 and the playback amplifier 10. The device also contains the second multiplying group 11. integrators 12, threshold elements 13, output recorder 14, pseudo-random signal generator 15. The accumulator also includes a clock reproduction head 16, a clock amplifier 17, a movable carrier information 18, the recording amplifier 19. The outputs of register 4 are connected to the first inputs of multipliers 5. The outputs of which are connected to the inputs of the adder 6, the output of which is connected to one of the inputs of the multiplier 3, the other input of which is connected to the output of the code converter 2, and the output to the input records of accumulator 7, the information outputs of which are connected to the first inputs of multipliers 11. The outputs of multipliers I are connected to the inputs of integrators 12, the outputs of which are connected to the inputs of threshold elements 13. The second inputs of multipliers 5.- 64 and 11 -, - And connect enes to the outputs of the generator 15. .The inputs of synchronization code converter 2 and the input gene) Ator 15 is connected. The device operates as follows. When writing to the register, feature 1 is supplied with a code-acknowledged code, and to register 4, an information code is supplied. The control unit (not shown in the drawing triggers the movement of the storage medium 18. The sync pulses come from the reproducing head of the clock pulses 16 through the amplifier of the sync pulses 17 to the clock input of the code converter 2 and the pseudo-random signal generator 15 and control their operation. Pseudo-random signals generated at the generator outputs 15, in smart phones 5 are multiplied by permanent signals, outputted from the outputs of register 4 and representing the values of the individual bits of the information code. Output signals are mind knives 5 are fed to the inputs of the adder 6. The signal from the output of the adder 6 is fed to the multiplier 3 and multiplied by the pseudo-random signal generated by the output of the converter

2. The result of multiplication through the amplifier 19 is fed to the recording head 8 and is recorded on the carrier 18. When the signal is read, the signal from the playback head 9 through the amplifier 10 is fed to the first inputs of multipliers ll. the second inputs of which receive signals from the outputs of the generator, pseudo-random signals 15. The generator 15 is synchronized by pulses from the reproducing head of clock pulses 16 through the amplifier 17. The signals from the outputs of multipliers 11 are integrated by integrators 12. The output signals of integrators 12 are converted in threshold elements 13 and the result in the form of a code enters the output register 14. The positive effect of the described device is the design hardening — the number of links is drastically reduced, the number of cleverly rer and adders digital storage medium is replaced by a continuous, movable, which leads to a significant reduction in cost of the device. An associative memory device containing a characteristic register whose outputs are connected to information inputs of a code converter. An input register, first and second groups of multipliers, a sucmator, a memory whose information outputs are connected to the first inputs of multipliers of the second group, the output register whose inputs are connected. to the outputs of the threshold elements, o. t., and in particular with the fact that, in order to simplify the device, it contains an additional multiplier, a pseudo-random signal generator and integrators, the outputs of the input register. connected to the first inputs of the multipliers of the first group, the outputs of which are connected to the inputs of the adder, the output of which is connected to one of the inputs of the additional multiplier, the other input of which is connected to the output of the converter codes, and the output to the input of the accumulator, the outputs of the multipliers of the second group are connected to the inputs-integrators, the code of which is connected to the inputs of the threshold elements, the second inputs of the group multipliers are connected to the outputs of the pseudo-random signal generator in, a, the synchronization input of the converter of the codes and the input of the pseudo-random generator

signals are connected to the synchronization output of the drive.

Sources of information taken into account during the examination 1. Korneychuk V.I. Zapomakihdiye

Kiev, Technique,

USSR certificate 11 from 15/00, 1974,

N f

D-DH

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