SU760452A1 - Injection-type modulo three adder - Google Patents

Description

The invention relates to a microele. ktronnoy technology and can be used to build logical circuits of a high degree of integration.

A known modulo two 5 injection type, containing transistors of three types of conductivity (pp—

-ρ-η-ρ-ηϊ р - η -metal) Schottky diodes {!].

The disadvantage of the known adder Modulo two is its complexity. ten

The closest technical solution to this invention is an adder modulo two injection type, containing eight multicollector transistors [2]. 15

The purpose of the invention is the simplification of the modulo two. .

This is achieved by the fact that, in the modulator adder, two injection types containing four multi-collector transistors, the bases of the first, second and third transistors are connected to the input buses and collectors, the fourth transistor emitters of the first, second and third transistors are connected to a common bus and to the base of the fourth transistor, the emitter of which is connected to the common bus through the power source, the first and second collectors. the first transistor connected 30

2

respectively, with the bases of the second and third transistors, and the first and second collectors of the second transistor are connected respectively to the first and second collectors of the third transistor and to advantageous buses, the collectors of the first transistor are connected to the input buses.

The drawing shows a circuit diagram of the proposed. modulo two.

Modulo two contains transistors 1-4, input buses-5-8, output 'buses 9-10, power supply 11.

'Structurally, the emitter regions of transistors 1-3 and the base of transistor 4 are common. There are also common bases of transistors .1-3 and, accordingly, three collectors of transistor 4 ’.

Modulo two works as follows.

Modulo two implements the exclusive-OR logical function

'(C = AV + AB), where C is the signal on output buses 9 and 10, A is the signal on input buses 5 and 6, B is the signal on input buses 7 and 8.

The logical unit is encoded .....

connection of the corresponding input or output busses to the common bus through.

3

760452

four

open and saturated transistors. A logical zero encodes the disconnection of the corresponding input or output bus from the common bus.

Work modulo two according to the signals on the input bus.

1. A “1, B = 1— at the input buses 5.8 the potential of the common bus, transistors 1-3 are locked, at the output buses 9.10 the potential of the logical zero”

2. А = 1, В = 0 - on the input buses 5,6 potential of the common bus, the input buses 7 8 are disconnected from the common bus, transistors 1 and 2 are locked, ^ transistor 3 is saturated, on the output buses 9,10 the potential of the logical unit .

3. A = 0 ,. B = D - on the input tires 7.8 the potential of the common bus, the input tires

5.6 are disconnected from the common bus, transistors 1 and 3 are locked, transistor 2 is saturated, on the output buses 9.10 the potential of a logical unit.

4. А = 0, В = 0 - input buses 5 8 are disconnected from the common bus, the collector current of transistor 4 unlocks the transistor

1. As a result, on its collectors, 25 connected to the input tires 6.8, the potential of a logical unit. This potential is transmitted to the base of transistors 2 and 3, locking them. At the output tires 9,10 a potential of logical zero is formed. ™

Thus, the present invention allows to realize the logical function "Exclusive OR", on four transistors tipap-ρ-η and pp-p, which is why it is implemented by a simple standard technology of injection integrated circuits.

Claims (1)

Claim Adder modulo -. two injection type, containing four multi-collector transistors, the base of the first, Ι '* of the second and third transistors are connected to the input buses and collectors of the fourth transistor, the emitters of the first, second and third transistors are connected to the common bus and to the 15th base of the fourth Transistor, the emitter of which is connected to the common bus through the power supply, the first and second collectors the first transistor is connected respectively to the bases of the second 20 and third transistors, and the first and second collectors of the second transistor are connected respectively to the first and second collectors of the third transistor and to the output buses, characterized in that, for the purpose of simplification, the collectors of the first transistor are connected to the input buses.