SU756399A1 - Device for interfacing digital computer with special-purpose calculators - Google Patents

Description

The invention relates to the field of computer technology and can be used as an effective communication device between a shared digital computer with values and a multitude of computer machines and, in particular, as a memory of a digital integrating machine (CIM) of a parallel structure.

Memory devices [1] are known, which can be used to store the values of the integrand in a parallel CIM, using different addressing modes, but having narrow functionalities that do not allow them to be used as a communication device between a digital computer and a CIM.

The closest technical solution to this invention is a device containing a register ad- "Resa, connected by an information input to the output of a digital computer, and the output to a block of decoders and drivers, a drive connected by address buses to a block of decoders and drivers, and bit to the playback amplifier unit and the recording pulse formers, the number register, the first information output and input of which are connected to a digital computer, and the second-30

ten

rye - with a block of playback amplifiers and pulse shapers ι records, a control block connected by control connections to the number and address register, a block of decoders and shapers, and a block of playback amplifiers of recording pulsers £ 2 ^.

The disadvantage of this device is limited functionality, which consists in the organization only derived access to numerical memory cells.

The aim of the invention is to expand the functionality by organizing the operation of the device in the mode of cyclically bit circulation.

This goal is achieved by the fact that the device containing the address register, the input of which is the address input of the device, and the output through the decoder is connected to the first input of the address generation unit; the register of the number, the first input and output of which are the first conformational inputs. and the device outputs, and the second information input and output are connected to the first output and input of the block of buffer registers, the second input

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and the output of which is the second information output and input device; a control unit whose outputs are connected to the control inputs of the number register, the register register of the buffer register register, the accumulator, two switches and a pulse distributor are entered, the outputs of the pulse distributor are connected to the corresponding inputs of the address generation block whose output is connected to the input of the first switch, the first and the second outputs of which are connected respectively to the address and informational inputs of the drive, the address and informational inputs-outputs of which are connected respectively to the first and the second inputs - the outputs of the second switch, the third input-output of which is connected to the input-output of the block of buffer registers, the control inputs of the pulse distributor, the first and second switches are connected to the corresponding outputs of the control unit.

The scheme of the proposed device is shown in the drawing and consists of a drive 1 connected to the first 2 and second 3 switches, ι block forming address 4, connected by the first information input to the output of the pulse distributor 5, address register 6, register number 7, the first information output and the input of which is connected to a digital computer 8 connected to the input of the address register b, and the second information output and input to the block of buffer registers 9 connected to a number of specialized computers 10 and the second switch 3 of the control unit 11 connected to all blocks and registers. the device synchronization connections and control outputs 12 and 13 are connected to blocks 4 and 9 and switches 2 and 3, decoder 14 connected to the output of address register b, and output to block of address formers 4. '·

The device operates in two modes;

in the mode of information exchange of digital computers 8 with specialized computers 1 0;

in the solution of specialized solvers 10.

The first and second modes are set by the control unit 11 signals, formed respectively at the outputs 12 and 13.

In the first mode, DVR 8 transfers the address to the address register 6 and the number to the register of the number 7; In accordance with the address code, the decoder and the address forming unit 4 through the first switch 2 selects memory elements along one of the longitudinal (horizontal) buses of the drive. Then, using the transducer of write pulses (not shown) on the transverse (vertical) tires of the drive into the selected memory elements, the code of the number stored in register 7 is recorded through the second switch 3. ‘

Similarly, information is read from the drive with the only difference that the read number enters the drive’s vertical tires through switch 3 to the inputs of the block of buffer registers 9 and then through the register of number 7 is transmitted to the digital computer.

Thus, the first mode is a normal operating mode of a digital memory computer.

In the second mode, with the help of the distributor 5, the block forming the adress 4 through the switch 2 performs a cyclic sampling of the vertical (transverse) tires of the accumulator 1.

The read information from the memory elements belonging to the corresponding vertical bus, via horizontal (longitudinal) tires, passes through the switch 3 to the inputs of block 9, from where it is transmitted to specialized calculators 10.

In the recording cycle, information from the output of specialized calculators 10 is fed to the inputs of block 9 and through the switch 3 via horizontal tires is recorded in the memory elements of the vertical bus selected by the distributor 5.

Thus, in the second mode, the information of all specialized calculators 10 is processed simultaneously, but in each calculator information is circulated sequentially through its buffer register of block 9.

For a better understanding of the drive in these two modes, we consider a matrix representation of the placement of information in it:

^α ιι- ^α ιπΊ l α. α α ” GM P1 'ΠΤη η and □ ί -I

where a. ¹ , o / ... C * n "column η-dimensional

1 * matrix row vectors;

a ¹ 'a'ya ... 01 line of t-dimensional

column vector of matrix.

The number of rows of this matrix, P, determines the number of specialized solvers connected to the drive, and the number of columns of the RL determines the length of the discharge grid of the memory cell (register) of the calculator.

In the solver's solver mode (second mode), each αι 'column vector ^: ("e) contains information

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tion of the vth weight of the numbers of all calculators, for example, the elements <3 ^, and _{in <>} . . .O "n4 of the column vector 0 ('| contain the first digits of all calculators, the elements ι ^α π1“ the second digits, etc., and the element ^ is the first digit of the first calculator, an4 of the last · ηth calculator and the element ace | Oh, <l

In the first mode (in the mode of information exchange between digital computers and calculators), each vector row, (ιε ^ η ^) is the number of the corresponding ιth calculator, for example, the elements cj ^, O ^ r - ^ rn of the vector-lines СЦ make up the number of calculating elements ^{α 2ΐ »α υ ·· ° ^} 2ΐΒ second calculator and 'the like, the element has a first discharge and OC _t last digit of the first calculator and · ^ € ^ 0,1).

Thus, in the first mode, the matrix of initial values is entered into the storage drive, and in the second mode, the operation with the transported matrix occurs.

The device allows you to very effectively organize the connection of a digital computer with a variety of special calculators by organizing not only an arbitrary appeal to the longitudinal cells of the drive, but also organizing a cyclic reference to the transverse cells of the drive using the same control schemes, and you can use known drive designs as a drive magnetic and semiconductor storage devices.

Claims (1)

Claim A device for interfacing a digital computer with specialized computers, containing the address register, the input of which is the address input of the device, and the output is connected via the decoder to the first input of the forming unit addresses, number register, the first input and output of which are the first information inputs and outputs of the device, and the second information input and output are connected to the first output and input of the block of buffer registers, the second input and output of which are the second information input and output of the device. a control unit whose outputs are connected to the control inputs of the number register; address register, buffer register block; drive, characterized in that, in order to expand the functionality due to the organization of the device operation in a cyclically bit circulation mode, it contains two switches and a pulse distributor, and the outputs of the pulse distributor are connected to the corresponding inputs of the address generation unit, the output of which is connected to the input of the first switch , the first and second outputs of which are connected respectively with the address and information inputs of the drive, the address and information inputs / outputs of which are connected enes with the first and second input-output switch, the third input-output of which is connected to the input-output buffer registers block control inputs of the pulse distributor, the first and second switches are connected to respective outputs bloka- control.