SU750469A1 - Multiplexor channel - Google Patents

Description

(54) MULTIPLEX K.NA,

one

The invention relates to digital computing and can be used for I / O information in digital computers and systems.

A multiplex channel is known, which contains the interface unit with the central processor unit, the central memory unit, the control register, the information register, the address modification and data counting unit, the local memory unit, the interface unit with external devices 1.

However, the known channel is not sufficiently effective in the systems for the transmission and processing of economic and statistical information, since in this case one has to programmatically compaction and decompression of the transferred data arrays, which requires the expenditure of machine time and an increase in the amount of RAM.

The closest technical solution to this invention is a multiplex channel containing a processor interface unit, the output of which is connected to the first input of the control register, the second input of which is connected to the output of the interface unit with external devices, input

which is connected to the first and third outputs of the control register, the first inputs of the interface block with the processor and the local memory block, the second input of which is connected to the second input of the control register via the access control block, the fourth output of which is through the address modification block and data accounts. x connected to the third input of the local memory block, to the output of the information register and the first input of the interface block with 10 RAM, the second input of which is connected to the output of the local memory block, to the third input of the register Regents and the second input register information, a third input coupled to vy.hodom unit interfacing with random access memory and the fourth control input of the register, a fourth output is connected to the input bytes in the word counting unit 2.

A disadvantage of the known channel is incomplete use of equipment.

The purpose of the invention is to enhance the functionality and increase the utilization rate of the kan equipment, a.

The goal is achieved by introducing a word and byte format changing block, word and byte formation control block, word bit comparison block and byte bit comparison block into the multiplex channel, and the fifth output of the control register is connected via the word and byte format changing block. with the input of the control unit forming the words and bytes, the output of which is connected to the first inputs of the comparison block of the word bits and the comparison block of the byte bits, the second input of which is connected to the output of the information register, the first in od is connected to the output of the comparison unit word bits, the second input of which is connected to the output interface unit to external devices, an input coupled to the comparison unit output bits of a byte, a second input unit izmene1i word format bytes and is connected to an additional input device. The drawing shows a block diagram of a multiplex channel.

The multiplex channel contains a processor interface unit 1, a memory interface unit 2, a control register 3, a word word comparison unit 4, a word count unit 5, a word and byte format change block 6, an information register 7, a block 8 controls the formation of words and bytes, the control block 9, the address modification and counting block 10, the byte bit comparison block 11, the local memory block 12, the interfacing unit 13 with external devices.

Multiplexed dripping works as follows.

It is controlled by instructions and performs all operations defined by the system of commands of the Unified system of electronic computing machines (EC computers) for inputting information.

The operation of the multiplex channel is initiated by the instruction "Start I / O, entering, it, from the processor to the interface unit with the processor 1; in this case, the address of the external device is fixed on the control register 3.

At the address of the external device, control register 3 starts, via the interface with external devices 13, the external device is sampled. Simultaneously, the external device is sampled at the address of a fixed cell from the control register 3 through the address modification and data counting block 10 and the memory interface 2 is read the address spruce of the channel (ACK). The ACK is fixed to the control register 3.

Next, the channel control word (CSC) is selected at the address in the ACK via the block 2 of interfacing with the operational memory. Simultaneously with the appeal to the RAM for the UIC, the modified UIC address is recorded in the block 12 of the local memory in

a subchannel cell for storage. Synchronization is effected by signals entering the local storage unit 12 from the processing control unit 9.

The address of the local memory location is formed at the first output of the control register 3. Selected from the RAM through the block 2 of the interface with the RAM UIC is also recorded in the corresponding bits of the register 3 control. External interface unit 13 compares the address received from an external device in the sequence of the initial sampling and sends a command from the control register 3 to the input-output interface. The byte received from the interface is in the interface 13 block with external devices. They are also analyzed for the occupation of the external device. At the same time, a record is made in the local memory unit 12 of the USK in the cells allocated to this subchannel for control information. For the operator "Write to the data address stored on the control register 3, the address management unit 9 and the memory interface unit 2 call the central RAM memory for the first data word. The word is fixed on the information register 7, the first byte of data is formed in block 11 of the byte bit comparison, and transmitted through the block 13 of the interface with external devices to the external device. The filling of a byte is determined in the block b of changing the format of words and bytes by the value of the corresponding bit in the USK or by the external control signal. According to the corresponding signal from block 6, changing the format of words and bytes, block 8 controls the formation of words and bytes and issues in block 11 a comparison of byte bits a control signal by which a byte is formed to be sent to block 13 to interface with external devices. Next, the byte counting unit 5 in the word changes its value by 1.

The continuation of the data exchange begins after the appearance of the request (TRB-A) on the I / O interface line. After the interface block 13 is fetched by the address that requested the external device, its address is recorded on the control register 3, the upper bits of which are used to retrieve the subchannel control information from the local memory block 12.

Junior address bits are equal to "O. When transmitting the last byte in the word to the external device (the signal about this event is generated in the control block 8 for forming words and bytes, the address modification and data counting block 10 modifies the address at which memory is accessed for a new word.

five

In the operation "read from the I / O interface, through the interface unit 13 with external devices, the byte enters the word bit comparison unit 4, which compresses the byte (the allocation of significant bits) and sends the corresponding signal of the word formation unit and control byte 8 it in the corresponding bits of the register 7 information. The byte count unit 5 in the word changes the word count value to "1", after which the value of the information register 7 and the control register 3 are written to the local memory block 12. Block 8 controls the formation of words and bytes on the signals of blocks 5 of counting bytes in a word and changing the format of words and bytes b determines the time when the formation of the word is completed and allows accessing the operational memory for the record generated on register 7 of the word danyl information, modification of the address and account data, writing the modified value of the control information into the local storage unit 12.

Claims (2)

Invention Formula A multiplex channel containing a processor interface unit, the output of which is connected to the first control register input, the second input of which is connected to the output of the interface unit with external devices, the input of which is connected to the first and third outputs of the control register, the first inputs of the processor interface unit and a local memory block, the second input of which is connected to the second control register input through the access control block, the fourth output of which is connected to t via the address modification and data counting block etim .mestnoy input of memory output data from the register and the first input unit operative mating with pa.m Tew. the second input of which is connected to the output of the local memory unit, to the third input of the control register and the second input of the information register, the third input of which is connected to the output of the interface block with the RAM and the fourth input of the control register whose fourth output is connected to the input of the byte counting unit in a word that is different from the fact that, in order to expand the functionality and increase the equipment utilization rate, the channel additionally contains a block for changing the format of words and bytes, a control block word and byte word block 5 comparison of word bits and a block of byte bits comparison, the fifth output of the control register is connected via an input block of the word and byte control block, the output of which is connected to the first inputs of the bit comparison block word and block of the byte bit comparison, the second input of which is connected to the output of the information register, the first input of which is connected to the outputs of the bit comparison block of the layer, the second input of which is connected to the output of the interface block with external devices, It is connected to the comparing unit output bits byte, a second input word format changing unit and the byte is connected to an additional input device. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 521559, cl. G 06 F 3/04, 1973. 2. USSR author's certificate No. 545079. class. G 06 F 3/04, 1978 (prototype).