SU705647A1 - Injection ik flip-flop - Google Patents

Description

(54) INJECTION JK-TPHrrEl

..- I The invention relates to the field of computer technology and can be used to create semiconductor integrated circuits. Known designs of injection triggers, made but multi-collector transistors, and containing the main and auxiliary trigger (1 |.. Their disadvantage is the low speed. The closest to the technical essence is an injection ZK-trigger, which is connected to a common transistor bus, the base of the first and second transistors are connected to the first and second counting inputs and inputs K and J, respectively, the first collector of the first transistor is connected to the base of the third and first call ctorv four, the first collector of the second transistor is connected to the base of the fourth and the first collector of the third, the second collectors of the first and second 7 |) amnstors are connected to the bases P.NATOGR l juecTorp transistors respectively and the first collector of the sixth - with the base of the eighth and first collector of the seventh transistor, the second collectors of the seventh and eighth transistors; The ditch is connected to the output buses Q and Q, respectively {2). The disadvantage of this trigger is the low speed associated with the need to switch four transistors before the signal appears at the outputs Q and Q. The aim of the invention is to increase the speed. The goal is achieved by the fact that the bases of the seventh and eighth transistors are connected to the third and fourth counting inputs, respectively, the second collector of the third transistor is connected to the base of the sixth, BTOpbiM collector of the fifth and third collector of the eighth transistor, and the second collector of the fourth - to the base of the fifth, the second

the collector of the sixth and third collector of the seventh transistor, the third collectors of the fifth and sixth transistor are connected to the Q and Q buses, respectively, the fourth collectors of the fifth and eighth transistors are connected to the base of the second transistor, and the fourth collectors of the sixth and seventh transistors to the base of the first.

.In FIG. I presents an electrical circuit diagram of an injection PC trigger; in fig. 2 - time diagrams of his work; in fig. 3 - basic electrical circuit of the trigger on single-collector transistors and Schottky diodes.

The injection JK-trigger contains the main trigger on transistors G-G4 and auxiliary trigger on transistors 5-g8. The emitters of all transistors are connected to a common bus. The base of transistor 1 is connected to K-input 9, and the base of transistor 2 is connected to J-input 10. The first collector of transistor 1 is connected to the base of transistor 3 and the first collector of transistor 4, the first collector of transistor 2 is connected to the base of transistor 4 and the first collector of transistor 3 The first collectors of transistors b and 7 are combined and connected to the base of transistor 8 and counting input 11, the first collectors of transistors 5 and 8 are connected to the base of transistor 7 and counting input 12. The second collectors of transistors 7 and 8 are connected respectively to output buses 13 (Q) and 14 (Q). The second collectors of transistors 1 and 2 are connected to the bases of transistors 5 and 6, the second collectors of transistors 4, 6 and 3, 5 and the third collectors of transistors 7 and -8, respectively. The third collectors of transistors 5 and b are connected respectively to buses 14 and 13, the fourth collectors of transistors 6 and 7 are connected to the base of transistor 1 with the counting input 15, and the fourth collectors of transistors 5 and 8 are connected to the base of transistor 2 and the counting input 16. The device operates in a loop. in a way.

The counting pulses arrive at the counting inputs 11, 12, 15, 16. The presence of four counting inputs in the JK-trigger is associated with that. that in injection circuits without base diodes it is not possible to combine the bases of switching npp transistors, therefore the input signal is supplied from the previous switching fourcollector npp transistor.

In the initial state (Q O, Q 1, K; L 1,) these transistors (1, 2, 7, 8) will be turned off, since the signal is supplied to their bases, the signal C 0. Transistors 7- and b, and 8 and 5 are connected by the scheme OR - NOT, therefore, in order for the signals at the outputs Q and Q to be equal to Q О, Q 1, the transistor 6 must be turned on and the transistor 5 turned off. This is ensured by the off state of the transistor 3 and the on state of the transistor 4 in the initial state.

} With the arrival of the logical 1 signal on the counting input, the main trigger switches; the transistor 2 is turned on, which leads to the switching off of the transistors b and 4 and then turning on the transistor 3. At the same time, the transistor 7 is also turned on, and the signal at the output Q remains equal to a logical zero, and at the output Q it is a logical one. In this case, the state of the trigger does not change. With the arrival of a logical zero signal, the transistor 7 is turned off and, so

(5 as the transistor b is also turned off, then the signal at the output Q becomes equal to logical one. This causes the switching of the transistor 5 and therefore, at the output Q, a signal of logical zero appears.

The period of operation of such a trigger is obtained from the time of recording information in the main trigger (turning on transistor 2), the turning off time of transistor 4, time. neither the inclusion of transistor 3 and the time ne2 $ of information transfer to the auxiliary trigger.

Claims (1)

Invention Formula Injection JK-trigger, performed on eight transistors, the emitters of which are connected to a common bus, the base of the first and second transistors are connected to the first and second counting inputs and inputs K and J S, respectively, the first collector of the first transistor is connected to the base of the third and first collector of the fourth, the first collector of the second transistor is connected to the base of the fourth and first collector of the third, the second collectors of the first and second transistors are connected to the bases of the fifth and sixth transistors, respectively. connected to the base of the seventh and the first collector of the eighth, and the first collector of the sixth - with the BA5 of the eighth and the first collector of the seventh transistor, the second collectors of the seventh O and the eighth transistors are connected to output Q and O, respectively, characterized in that, in order to improve performance, the bases of the seventh and eighth transistors are connected to the third and fourth counting inputs, respectively, the second collector of the third transistor is connected to the base of the sixth, the second collector of the fifth and third collector of the eighth transistors, and the second collector of the fourth with the base of the fifth, the second kaalector of the GPS and the third collector of the seventh transistor, the third collectors of the fifth and sixth TpaicuicTopeB are clutched with Q and Q spikes, respectively, the fourth collectors of the fifth and eighth transistors are connected to the base of the second transistor, and the fourth collectors of the sixth and seventh transistors are connected to the base of the first. Sources - information taken for examination during examination 1. Patent of Germany No. 2442773, cl. H 03 K 3/286, 09/06/74. publish 03/18/76. 2. “1EEE. ISSCC Digest of Technical Pa per. 1976, p. 100 (prototype).