SU701349A1 - Associative memory - Google Patents

Description

(, 54) ASSOCIATIVE BAnOMllHAIOtHEE DEVICE

The device contains (see, Fig. 1) address memory blocks 1 arranged in the form of a rectangular matrix.

Each unit 1 contains, for example, four address storage units 1.1-1.4 or 1.5-1.8 (see FIG. 2), which can be made in the form of semiconductor chips. Blocks 1.1-1.8 have address buses 2, output bit buses 3, bit buses 4. Records, sample control inputs 5, record control inputs b, information inputs 7. In addition, the device contains register triggers 8 and 9 10 polling and register 11 masks, respectively, which are divided into groups of 12 triggers 8 and group 13 of triggers 9 by the number of rows of the matrix, elements OR 14. The first inputs 15 and the second inputs 16 elements OR 14 are connected respectively to the direct outputs 17 and reverse outputs 18 flip-flops 8 poll register 10 and direct outputs 19 flip-flops .9 regis pa mask 11, and outputs - to the inputs 20. The outputs of decoders survey decrypts the tori 20 are connected with the address bus 2 .mi units 1 of respective rows of the matrix.

Register 11 masks, elements OR 14, and decoders 20 are divided into control groups 21 by the number of blocks 1.1-1.8 in block 1.

Inputs 5, 6 and 7 of blocks 1 of each column of the matrix are connected to the outputs of the decoder 22 operations. Bit bus 4 records of blocks 1 are connected to the outputs of adders 23 modulo two, the first inputs of which are connected to the corresponding outputs of the decoder 22 operations. Group 13. trigger 9 register 11 made in the form of a circular shift registers. The device also contains two-channel switches 24.

The first inputs of the adders 23 are connected to the corresponding outputs of the decoder 22.

The outputs of the switches 24 are connected respectively to the second and third inputs of the adders 23, and the control inputs of the switches 24 and the adders 23 to the corresponding outputs of the decoder 22.

The inputs of the switches 24 are connected to the output bit buses 3 of the respective blocks 1.1-1.8 (see. Fig. 2).

In order to increase productivity when performing multiply and divide operations, the device may contain the first additional two-channel switches 25 (see Fig. 3), the second additional two-channel switches. switches 26 and elements AND 27. Each block 1 contains additional address blocks 1.9, 1.10. or 1.11, 1.12.

The operation of the device shown in FIG. 1 and 2, let us illustrate by the example of performing the operation of adding two groups of four four-digit numbers with eight blocks 1.1-1.8. Each of these blocks in this example has four address buses 2 and four bits 3 and 4. Four numbers 0001 are written in blocks 1.5 and 1.1, UN, 1011,0111, and in blocks 1.6 and 1.2 there are four numbers

1011, 0111, 0100, and 0101. The two least significant bits of each number are in blocks 1.1 and 1.2, and the two high bits in blocks 1.5 and 1.6. The indicated numbers are written on the corresponding bits of the lines of these blocks, i.e. in storage elements connected to one of the buses 3 and 4, in code 1 of N (1 against the background of N-1 zeros). Conversion from the position code to code 1 from N is performed by decoder 20. Code 1 is pre-recorded in all storage elements of blocks 1.7, 1.3, 1.8 and 1.4, the count of outputs of decoders 20 starts from the bottom, and the count of numbers is from left to right:

In the first clock cycle, the registers 10 of the first and second lines of the survey register code 11, and on registers 11 masks corresponding to blocks 1.1-1.3 and 1.5 - 1.7, code 10 hours to registers 11 corresponding to blocks 1.4 and 1.8,. As a result, blocks 1.1. - 1.3 and 1.5-1.7 addresses 01/11 are excited, and for blocks

1.4 and 1.8 - addresses 10, 11. A logical signal 1 is applied to the inputs 5 of all blocks allowing the access

to them, to the inputs 6 of the blocks 1.1, 1,2, 1.5, 1.6, a logical O signal, allowing reading from these blocks, and to the 6 inputs of 1.3, 1.4 and 1.7 and 1.8, a signal of logical 1, allowing writing to these blocks. Blocks 1.7 and 1.3 are used to accumulate bits of money, while blocks 1.8 and 1.4 are used to accumulate transfers. The sum of the sum is formed by summing the pairs of source numbers modulo two, and the transfers — by logical multiplication of the pairs of source numbers shifted by one digit to the left (meaning the shift of the source positional codes of numbers).

When performing a modulo-two operation, the control inputs of the adders 23, corresponding to blocks 1.7 and 1.3, receive signals d О, and when performing the logical multiplication by the control inputs of the adders 23, corresponding to blocks 1.8 and 1.4, signals. The first inputs of these adders in the first and second cycles: signals are received from 1. Switches 24 connected to buses 4 of blocks 1.3 and 1.7 are constantly switched by signals at control inputs to receive signals from blocks 1.1, 1.2 and

1.5 and 1.6 in order for the bit amount to be written in blocks 1.3, 1.7 without a shift. In the first cycle, the switches 24, the corresponding blocks 1.4 and 1.8, also commute to

receiving information from blocks 1.1, respectively. 1.2 and 1.6, 1.5. The shift of the result of the logical intelligence operation is due to a cyclic shift by one bit of the mask code of blocks 1.4 and 1.8 relative to the mask code of blocks 1.1, 1.2 and 1.5, 1.6. After the first cycle has been completed, blocks 1.3, 1.7 and 1.4, 1.8 contain the following information:

1.7

1.8 ITO 0001

1111

0001

o

0111

1111

1111 1111

1.3

1.4

five

0010

1101

nil

1101

0010

1111

0

1111 1111

In the second cycle, the codes in the registers 11 of the mask are shifted cyclically 01

5 for blocks 1.1-1.3 and 1.5-1.7 and blocks 1.4 and 1.8, and switches 24, corresponding to blocks 1.4 and 1.8, are switched to receive information with a shift of one line.

0

In the third and fourth clock cycles, the first inputs of the adders 23 receive signals, the second inputs of the switches corresponding to block 1.4, the signals of logical 1, and

5 register 10 polling of both lines is code 00, and the mask codes are cyclically shifted in each cycle. The signals at the second inputs of these switches 24 are inverse (inverse) to signal C.

0

In this case, in the third cycle, the shift of the transfer result is obtained due to the shift of the mask codes of blocks 1.1–1.3 and 1.5–1.7, and in the fourth cycle, due to the shift of the mask codes and

5 switching switches 24, corresponding to blocks 1.4 and 1.-8, which is similar to the second cycle. The diagrams of the state of modules 1.3, 1.7, 1.4 1.8 in the 2nd, 3rd and 4th cycles are given below.

001000000010000000100000

101000011000000110000001

011001000110010001000100

Claims (2)

111111111001 111000011010 A direct comparison of the results of performing the fourth cycle with the results of modulo two addition and logical multiplication of positional codes confirms the correctness of their computation. Since the content of blocks 1.4 and 1.8 differs from the position code 0000 or the word 00010001 in code 1 of N, the addition operation continues in the same way until the transfer codes completely coincide with the code for all numbers involved in this addition operation. . To do this, in all the storage elements of blocks 1.5, 1..1 and 1.6, 1.2, write code 1 and perform a pairwise addition of the contents of blocks 1.7, 1.3, 1.8, 1.4, etc. A check for the equality to zero of all transfers can be performed by polling blocks 1.8, 1.4 or, 1.6, 1.2 by polling code 0000. The device shown in FIG. 1 and 2 ,. can be used to perform all logical operations on two variables. When performing operations of equivalence and logical addition in the first two cycles to the first inputs of the adders 23, signals are given, and in the next two cycles, signals are given. For you. For operations with inverse number codes, control groups 21 are used in which polling code 11 ... 1 can be replaced with code 00 ... O, for example, by introducing an independent register 10 into each group 21 of each of the 21 groups. survey. The rewrite in the direct code is performed as modulo two addition with the code 0000, and the inversion operation is performed as modulo two addition with the code llllj. The subtraction operation is performed, kick splitting with the reverse or additional {of the deductible, the floating point operations are performed similarly to the operations in the floating point totalizers, i.e. due to the introduction of associative bits, the equivalent of a valence table to an order adder, which function similarly to the device shown in this example. The operation of the device shown in FIG. 3 differs from the operation of the device shown in FIG. 2 in that the blocks 1.9-1.12 are used to shift the multiplicand and multiplier codes, respectively, one bit to the right and left. Multiplication is realized by accumulating in the modules 1.3, 1.7 the sums are sequential ;: shifts of the codes recorded in blocks 1.10, 1.12, in accordance with codes 1 on the corresponding buses 3 blocks 1.9 of each column of the matrix. Blocks 1.1, 1.5, 1.2, 1.6 are used to store intermediate results. Multiplication begins with entering the multiplier codes into blocks 1.9, 1.11 ... and 1.10, 1.12. Then, the codes of these factors are shifted by one bit with the final result recorded in blocks 1.9, 11 and 1.10. 1.12 and rewrite the contents of blocks 1.10, 1.12 into blocks 1.4, 1.8. In blocks 1.3, 1.7, ..., words with the position code 00 are pre-recorded. Next, the contents of blocks 1.3, 1.7 ,, .. and 1.4, 1.8, ... are added together with the final result recorded in blocks 1.3, 1.7. Then the codes are shifted in blocks 1.9-1.12 by one more bit, the contents blocks 1.10,1.12 is rewritten into blocks 1.4 n 1.8 and summed with the contents of blocks 1.3 and 1.7. otherwise, the execution of the multiplication operation in this device is similar to the execution of; and multiplication in a normal adder. The division can be replaced by subtracting the contents of blocks 1.10 and 1.12 from the contents of blocks 1.3 and 1.7. The use of the described device allows parallel execution of logical operations, arithmetic addition, and subtraction operations. multiplying and dividing over two arbitrary arrays of numbers, and these operations can be performed in various combinations, one independent operation for each column of the matrix. Consequently, the speed of this device in comparison with the known devices with the right choice of the algorithm for writing initial arrays increases by one to two orders of magnitude and can be evaluated in a few tens of millions of operations per second for a device with a capacity of 10244096 words for 18-72 bits. Yes, with a single polling cycle and recording on the order of 200 NS. An associative memory containing a matrix of addressable memory blocks, OR elements whose inputs are connected to the polling register and mask register outputs, and outputs to the polling decoder inputs, whose outputs are connected to the address buses of the memory address blocks of the corresponding matrix rows, cipher cg. 1 torus of operations, the outputs of which are connected to the inputs of the control of sampling and recording and the information inputs of the address memory blocks of each column of the matrix, modulo adders whose two outputs are connected to discharge write busses of address memory blocks, and the first inputs to the corresponding outputs of the operation decoder About t-l and chuyu e so that, in order to improve the device's performance, it contains two-channel switches, the outputs of which are connected to the second and third inputs of modulo-two adders p dnymi tires respective address blocks of memory, control inputs of the two-channel switch and two modulo adders are connected to corresponding outputs of decoder operation. Sources of information taken into account in the examination 1, USSR Author's Certificate No. 493162, cl. G 11 C 15/00, 1974. 2. USSR author's certificate №588561, cl. G 11 C 15/00, .1975 (prototype). Oj im