SU693275A1 - Device for registering short-circuitings and breaks of internal leadouts of transistors - Google Patents

Description

(54) DEVICE FOR FIXING SHORT CIRCUITS AND CURVES OF INTERNAL OUTPUTS OF TRANSISTORS

one

The invention relates to electronic engineering and can be applied to control the quality of semiconductor devices in the manufacturing process.

A device 1 is known for capturing short circuits and breaks in the internal leads of transistors, comprising a current source, a resistor, a voltage source, an amplifier, a trigger, an indicator. In this device, when tested, the transistor is in an amplifying mode. During the mechanical tests in the test transistor, a short-term or permanent break or short circuit of the internal leads of the transistor may occur, which will cause a sudden change in the electrical mode of the test transistor, which is fixed by this device.

It is also known a device 2 for fixing short circuits and breaks in the internal leads of transistors, comprising a source of a rectangular voltage, a resistor, a trigger, an indicator, a voltage limiter, an electronic switch, a linear amplifier.

In this device, the amplifier under test is set to the test transistor. A jump-like change in mode caused by the appearance of a defect (short circuit or interruption of internal terminals) during

mechanical testing is amplified by the amplifier and fixed by a trigger, as indicated by the indicator.

In this circuit, the transistor, when tested, is in the amplifying mode and a pulse amplifier is switched on between the output of the transistor and the trigger input. Such a circuit has a low noise immunity due to the fact that when interference occurs at the input of the transistor, it is amplified by the test transistor and amplifier of pulses, which in many cases is enough to cause the trigger to tip. This device cannot detect a short-term break in the output of the gate of a MOS field-effect MOS transistor arising during the test, due to the long time constant of the gate-source input circuit, which is inherent in the field-effect transistors.

The purpose of the present invention is to increase the noise immunity of the device,

This goal is achieved by introducing a inhibit circuit into the device, the signal input of which is connected to the output of the square voltage pulse generator, the control input connected to the output of the tested transistor, and the output of the inhibit circuit connected to the trigger input.

The drawing shows the block diagram of the device for fixing short circuits and breaks of the internal terminals of the transistors.

The device contains a generator 1 of rectangular voltage pulses, a limiter 2, a source of a constant voltage 3, a resistor 4, a prohibition circuit 5, a trigger 6, an indicator 7. The transistor under test is indicated in the diagram by the figure 8.

The device works as follows. .

The input terminal of the test transistor 8 from the output of the generator 1 rectangular voltage pulses receives rectangular pulses. The amplitude of the pulses is set such that the transistor under test operates in a key mode (open-closed), and the resistor 4, which is the load of the transistor under test, produces rectangular voltage pulses applied to the control input S of the inhibit circuit 5. The signal input And the inhibit circuit 5 is supplied with voltage pulses from the generator 1. The inhibit circuit operates in such a way that the signal applied to the signal input A causes the appearance of the signal at the output P only when there is no inhibitory signal on the control The entrance of S.

When a transistor is tested for mechanical strength, its performance may be impaired due to either a break of one or several of the terminals or a short circuit between the terminals. When a source is short-circuited, a source-gate, a gate-drain, as well as one or more terminals are broken at the load resistor 4 at a point. The voltage pulses disappear. The disappearance of pulses at the control input of the inhibit circuit causes a pulse at its output P. This pulse triggers trigger 6 to another steady state, as indicated by indicator 7. In the case of testing MOS field MOS transistors in key operation mode, when the gate direct bumper voltage pulses are supplied, the gate-source input capacitance does not affect the mode, since it is periodically charged — discharged through a small output impedance of the generator. When the gate pin is broken, periodic charging of the input capacitance stops, and hence the formation of pulses on the load resistor 4 at point M, which is indicated by the indicator. If the indicator turns on, it means that a short-term defect in the transistor was detected - an open or short circuit, but if the indicator remains on, then there is a permanent defect. Thus, the proposed device allows an operational determination of the nature of an existing defect. The duty cycle of the generator pulses is set to 2, the frequency is selected based on

.

where ij is the generator frequency,

T, efminimalna duration of the defect, which must be fixed.

Voltage limiter 2 is designed to limit the voltage at the input of the transistor at a level not greater than the maximum allowable.

Claims (2)

1. Transistors; parameters, methods of measurement and testing. Ed. I. G. Bergelson, M., “Owls. Radio, 1968, p. 365. 2. USSR author's certificate No. 446853, cl. G 01 R 31/26, 1968 (protot m -