SU691928A1 - Analog memory device - Google Patents

Description

(54) ANALOG STORAGE DEVICE

The invention relates to computing and computing, and is intended for sampling and storing instantaneous values of voltages, in particular, can be used in analog-digital converters.

Known analog storage device containing amplifiers, cumulative element and keys. The device is covered by two feedback loops 1.

However, the known device has insufficient speed due to the fact that with increasing gain of amplifiers the frequency band of the amplifiers decreases.

The closest in technical essence to the proposed is an ana South storage device containing the main storage element, for example, a capacitor, one lining of which is connected to the zero potential bus, the other to one of the inputs of each of the two amplifiers and through the first key to the output of the first amplifier V another input which through the second switch is connected to the input of the device Another input of the second amplifier is connected to the output

the first amplifier through the first matching element, and through the first feedback element is connected to the output of the given amplifier; the analog storage device also contains a third key, with a closed first and second key and an open third device covered by the first negative feedback circuit and is in sampling mode , The voltage on the capacitor and the output of the second amplifier is in phase with the voltage of the input signal and differs little from it in magnitude. With the third key closed and the others open, the device is covered by a second loop of negative feedback and is in the storage mode. Voltage from the output of the second amplifier

0 is fed to the input of the first amplifier. Since the characteristics of the first amplifier do not change from the sampling mode to the storage mode, this voltage is set in the storage mode to the same level as the high-voltage signal when the device switches from sample mode to storage mode. Devices built on e, the scheme, have a high point

in the best examples, the memory error was increased to 0.01%

2

However, at present, sampling and memory devices with an accuracy of up to 0.001% are required. Ensuring, with such precision, high speed becomes an extremely difficult task. Application to ensure: I high-speed broadband amplifiers leads to a decrease in the accuracy of the device, since such amplifiers have a low transmission coefficient, an increase in the gain of the amplifiers leads to a decrease in the frequency band of the amplifiers and, consequently, the speed of the devices.

The purpose of the present invention is to improve the accuracy of the device. ,

This is achieved by the fact that a third amplifier, a second feedback connection, connected between the output and the first input of the third amplifier, the second matching element, the fourth and fifth keys, and an auxiliary storage element, such as a capacitor, one of which is connected to the bus zero potential, and the other with the second input of the third amplifier and through the third key with the output of the second amplifier. The output of the third amplifier is connected to the output of the devices and through the fourth key to another input of the first amplifier, and through

where Ug is the input voltage (voltage at input 24 of amplifier 1); To - the transfer ratio of the amplifier 1.,

In the second stage, the voltage present on the capacitor 9 is memorized and becomes the input. It is balanced by a voltage, successively connected to the second matching element, the second feedback element and the fifth key to the output of the First Amplifier.

The drawing shows a block diagram of the proposed device.

The device contains the first amplifier 1, the second amplifier 2, connected by input 3 through feedback element 4 to output 5, and through matching element b to output 7 of first amplifier 1, input 8 to one plate of a capacitor 9 connected to the other facing of the bus zero potential 10, and to the input

11 the first amplifier, and through the key

12 to input 7 of the first amplifier 1, the third amplifier 13 connected by input 14 via feedback element 15 to its output 16 and output of device 17, and through matching element 18 and switch 19 to output 7 of the first amplifier 1; input 20 - to one plate of auxiliary capacitor 21, connected by another plate to the tire of zero potential 10; and through the key 22 - to the output 5. THE SECOND amplifier 2; and output 16 via switch 23 to input 24 of the first amplifier 1 connected via switch 25 to signal source 26.

The operation of the device occurs in 4 stages. The state of the keys corresponding to the stages is given in the table.

(p, -)

(-k, sr,)

:) ()

((i

.

i ((And + (. 1 (p2

 the gain of the amplifier 2 from the input 3; (3 is the transmission coefficient of the amplifier 13 from the input 20 side (with open key 19);

Pj is the gain of the amplifier 2 from the input side 8.

R4

 Z

p-l-L6

AR. + R, 2

4- t

de r

jr resistance of elements 4, b; .

Kg is the gain of the amplifier 2.

TO;

Pz rnr;

3 The transfer coefficient of the amplification of the bodies is 13., v Considering the equality of R4 and R - (- S, 5 to 2 {+0.54, Let us assume for simplicity K2, K togdar 1, (2 exp (2) take the form. () On the third At the stage, the voltage present on the capacitor 21 is remembered and the input voltage of the capacitor 9 U becomes equal to, (p) With regard to p), the expression (4) with the view and -and I 2 Pa fourth floor; voltage sources, the voltages present: capacitors 9, 21 (Uc U) are at the output of the device, the memory is found in NII,. (-K, .. PS., P4 transfer coefficient of the bodies 13 from the sides WMOs transmission coefficient of the body 13 by WMOs (when closed key F15 1 - e comrade resistances 15, 18 and the equality and Ri8 P4VTfo; FK7 0 1 + Ks and K p4 with 1, 2 p5.

(6) will accept a fork

Now expression

and -

.

In view of (1

, (3), (5) expression (7) is written

Гк (2 + К.) 2К.С2 + К 1

 S. (7TK; iVJ. {“;

From here there is an error of memorization.

 2K (

ten

-V-UB,

Claims (1)

1. Japanese Patent 6956, cl. 97/8 D 1, 1969, 2, USSR Author's Certificate 482815, cl. G 11 C 27/00, 1973 (prototype). m 13 -.21