SU691828A1 - Time count apparatus in a digital computer - Google Patents

Description

one

The invention relates to the field of computer technology and is intended for the construction of high-performance multiprogrammed electronic computers (COMPUTERS) operating in real time.

There are known devices of counting, time, or blocks of timers. Realized by software and hardware of a computer. In such devices, the generation of reference marks is done in hardware, and the contents of the timers are modified by the software supervisor using the ueHTpajibHoro processor 1J, 2. Each modification of the contents of the timer requires accessing the supervisor, which significantly reduces the performance of the computer high resolution.

The closest in technical essence to the proposed device is the EC 1050 computer timers block, which contains a time tagging node that is connected to the inputs of the I-YRI 3 circuits.

When organizing high-performance multiprogramming computing

Real-time systems require a block of timers that work simultaneously with real time scales. At the same time practically not; The costs of software (analog) or software / hardware (prototype) tools will acceptably increase.

The aim of the invention is the expansion of functional. Capacity due to the simultaneous operation of the device with different time scales.

The goal is achieved by inserting a matrix of switching triggers into the timer block, deciphering the number of subchannels whose input is the first input of the device, and go, connecting to the first control inputs of the switching matrices of the corresponding row, the decoder of the Timestamp Frequency Code, input which is the second input of the device, and the outputs are connected to the second control inputs of the switching triggers of the matrix of the corresponding column, the decoder of the feature whose input is the third input devices, and the output is connected to the installation inputs

matrix triggers and is the first output of the device, the fourth input of the device is the zeroing inputs of the switching triggers of the matrix, the outputs of the switching triggers of the matrix rows are connected to the second inputs corresponding to the elements of the AND-OR group, whose outputs are the second outputs of the device.

The drawing shows a block diagram of the device and its connection to the nodes of the multiplex channel. The dashed line indicates the nodes belonging to the actual block of timers. The device contains processor receiving instructions 1. Instructions receiving register 2, control device 3, subchannel 4 input memory assembly, subchannel 5 memory, queue circuit 6, subchannel number decryptor 7, subchannel memory address collection 8, an encoder 9, output assembly memory of subchannels 10, register of active subchannel II, exchange address 12, command address bus 13, data counter 14, terminal 15 address of the external device, bus of time frequency code 16, operation code 17, input adder assembly 18, adder 19 , communication node with RAM 20, communication buses with RAM 21, communication node with interface 22, interface 23 widths, interrupt signal widths 24, 25 control processor, RAM and channel control signals, totalizer 26 decipheror, accumulator trigger trigger reset 27, attribute decoder 28, switch setting trigger bus 29, subchannel number decaller 30, row selector control lines 31 of the matrix of switching triggers decoder 32 time tag frequency codes, selector control bus 33 of the switch trigger matrix 33, commutator trigger matrix 34, Soder ascha mxn triggers (T - number of timers, n - number of frequencies; in fig. 1 shows the matrix for the case of P1 p 2) the time stamper 35, the logic switch 36, containing n AND-OR circuits. 37 — first device input, 38, 39, 40 — second third and fourth inputs, 41 — first device output, 42 — second device outputs.

Here, nodes 1-26 belong to the multiplex channel, and nodes 27-36 belong to the time reference device in the digital computer.

The multiplex channel presented in the block diagram is the classical input-output channel of modern computers (for example, the computational masses of IBM-360, CM-370, EC-COMPUTER systems, etc.). Such a multiplex channel implements a two-way exchange between the operative memory of a computer and external devices (WU).

The possibility of parallel exchange with a large number of slaves is provided by the presence in the channel of special hardware, called subchannels. Each subchannel is a memory cell of subchannels 5, in which the device control word (CID) is stored, in accordance with which the channel organizes the exchange with the control unit for this subchannel. UCS format is shown below:

AVU KOP FL SCHD AK

AO

H

Here AVU is an external device address field

COP - opcode field

FL-field flags

NCC-field data counter

AK-field team address

LO - field address exchange

H is an unused field.

The subchannel is activated on the corresponding instruction from the processor or on demand from the slave: operating on this subchannel. When activating a subchannel, its CCD on the memory cells of subchannel 5 is entered into the register of the active subchannel 11, the logical connection of the multiplex channel to the slave is established; addressed in the CIC format, and an exchange session is performed.

The contents of the UCS format fields are intended to control the exchange.

The address field of the slave is used to select the desired slave, and also indicates the number of the subchannel to be used. The operation code field specifies three commands, and the flag field specifies special conditions when exchanging (command chain, data chain program-controlled interrupt, etc.). The data counter field is used to determine the end of the exchange after the transmission of a programmed amount of data. The command address field is used for addressing the main memory of the computer when storing the next SIC in the subchannel 5 memory, and the exchange address field is used for data exchange. An unused field is present due to the fact that the CCD format usually does not coincide with the format of a machine word. Therefore, in order to match the formats, an unused field is entered into the CCD so that the size of the CCD is a multiple of the size of the spread word.

The following prerequisites for a multiplex channel of modern computers were used to build the proposed timer block:

- the number of subchannels in the multiplex channel reaches 256, and in the majority of computer complexes some subchannels are not used for the exchange with WU; the equipment of non-used subchannels is idle;

- the initial value of the fields of the laiiHhix counters; the CIC is set programmatically;

- when a data word is transmitted over a subchannel, the contents of the corresponding data counter floor are reduced by I;

- when the data counter reaches zero (the "data counter has been exhausted"), an interrupt signal is generated;

-the current value of the data counter floor is available to the program, in. in particular, by transmission in the format of the channel state word.

The proposed device allows, with minor additional hardware costs, to organize a block of independent software timers based on unused subchannels of the multiplex channel. It should be emphasized that the possibility of organizing program timers on a number of subchannels of program timers does not in any way impede the possibility of organizing a normative exchange with a VU on these subchannels.

The code of the current value of each of the timers is the contents of the data counter of the corresponding subchannel. The programmable initial value of the counter is modified by I for each request pulse (FROM), simulating the exchange with the slave. The request pulses are the signals of the software-selected reference oscillator (internal or external).

To identify the timed operation of the subchannel, a sign of the timer is entered into the CCD. This feature can be encoded in the address field of the TDU, or in the field of the operation code, or by a special field in the field of the unused field. For a software task of one or another reference oscillator, according to the timestamp signals of which this subchannel operates and in timer mode, the timestamp frequency code field is entered into the UCD. This field is located in the bits of the unused ACM field.

The proposed block of timers operates as follows.

From the processor of the computer (in fig. Not shown) the bus I receives the instruction, which is entered into the register 2. At the same time, the control device 3 receives a signal from the processor that starts the channel. Instructions accepted on register 2 can belong to one of three types:

-start input-output (NVB);

-check input / output (PVV);

- to stop input-output (OVV). If the instructions are in register 2,

is a HBB instruction, then the control unit 3 selects the command into RAM, which, via the busses 21 through the node 20 and the assembly 4, is stored in the memory of the subchannels b. At the same time, the control unit 3 generates a request signal to the queue circuit 6.

The address of the memory cell of subchannels 5 is determined by the decoder 7, which decrypts the code of the address of the subchannel contained in the HBB instruction format and received at the inputs of the decoder 7 through assembly 8.

After the execution of the application from control unit 3, the encoder 9 generates the memory address of subchannels 5, which, through assembly 8, enters the inputs of depligraph 8, and the queue circuit 6 generates a start signal for control unit 3. Control unit 3 carries out reading out from memory the subchannels 5 of the CCD and entering it through assembly 10 into the register P.

If the CCD entered into register 11 does not contain a timer sign (an exchange with the slave is suggested), then further actions are carried out as in any of the traditional channels. .

If the CCP is designed to control the timers, which is determined by the VU number in}, the UCS format (i.e., in this case, the WU address field is used to identify the subchannel operation in the timer mode), the signal that blocks the execution of the control unit 3 of those microprogram sections that provide the output of numerical and control information to the slave unit through the node 22 to the scaffolds 23 and the RAM through the node 20 via the buses 21.

 Decoder 30 decodes the timer number code, and decoder 32 decodes the timestamp frequency code that this timer should work with. The signals from the outputs of the decoders 30, 32, respectively, across the buses 31, 33, enter the inputs of the installation of the triggers of the matrix 34 and provide a sample of one of them. The signal from the output of the decoder 26 (bus 27) sets the trigger to one state, and the signal from the unit output of this trigger opens one of the AND-OR schemes of the logic switch 36. Thus, the flow into the queue 6 from the formation node is allowed timestamps 35 signals selected by software

5 reference frequency. Thereafter, the contents of register 11 is entered through, assembly 4 in the m subchannels 5.

With the advent of the signal, the timestamp, the latter through the scheme AND-OR logical

 the switch Zb comes to the scheme, queue 6 as a request for service. Upon receipt of this application, the encoder 9 generates the binary code of the address of the memory channel of subchannels 5, which stores the CCD to control the operation of the timer. The address code through the assembly 8 receives the la inputs of the decoder 7, and the circuit 6 generates a signal on which the control unit 4 selects the timer UCS from the subchannels 5, enters it into the register 11 through the assembly 10 n modifies the word count value. Modification is carried out by adder 19, to the inputs of which the word counter code enters via the bus 14 via the assembly 18. Then, the exchange address is modified, the koporo code enters bus 12 through assembly 18 (modification of the exchange address is not a necessary procedure for the subchannel to operate in timer mode and is dried only to ensure uniform operation of the multiplex channel with the timer and WU). The modified ACCM is entered into the register 11 through the winding 10, and then through the assembly 4 is loaded into the memory of the subchannels 5 and the queue circuit 6 is reset. The queue circuit is reset to prepare it for service of the next application. .

When the word counters reach zero (the number of time stamps corresponds to the value specified in the UCS format) is served, decoder 26 generates a signal to control device 3, according to which the latter analyzes the contents of the UCS flags field currently in register P. If the box is checked The data chain (CSD), the control device 3 is the same. As in the case of servicing any, UMC selects the command with a new sign from the RAM. word count and loads it into the memory of subchannels 5,. The data chain mode (the presence of the CD flag) allows you to increase the number of samples to the required value. If the CS flag is not set, then control unit 3 generates an interrupt signal, which, on buses 24, enters the processor interrupt system and is the mark of the timer expiration. Regardless of the presence of CSD flags, when the word zero reaches the word counter, the decoder 26 generates a reset signal for the matrix trigger 34, which is nbctynai T into it via bus 27.

Highlight actions are characteristic for the operation of timers in the "alarm" mode (i.e., the program sets the time interval, after which the interrupt signal is generated).

The proposed device also provides an account of the current time. In this mode, it is necessary to ensure the possibility of the program’s on-line access to the data counter floor value. Such access is organized by executing a UIP instruction that sends the channel coctoHhH to RAM. The channel status word format contains a data counter field.

According to the HVD instruction, the channel stops working on this subchannel, regardless of whether it is serviced by a slave or a timer.

UHV and OVV instructions are followed.

 so same as in traditional computer channels. As well as when working with WU, multiplex channel when working with multiple timers ensures their simultaneous operation.

10 Thus, the present invention allows, by means of minor additional hardware costs, to implement, on the basis of unused subchannels of a multiplex channel, a block of software timers with the possibility of independent parallel operation, which ensures deep, highly efficient service of multiprogramming and multiprocessor computing systems.

Claims (3)

1. Drozdov, E. A., P Tibratov, A. K. [Foundations of the construction and operation of computer systems, M., Energia, 1973]. 2. Principles of work 1BM / 37Q edited by Raikov, LD, M., 1975, S 3. EC-1050 computer edited by Larionoya, M., Statistics, 1976 (prototype).