SU690565A1 - Storage element for associative store - Google Patents

Description

I

This invention relates to the field of technology, in particular to memory devices.

Memory elements are known in which information retrieval can be carried out on the basis of a limited number of functions of 2 variables and a significant number of transistors 1 are required to implement an associative search.

A storage element is also known, which contains a main and auxiliary storage capacitors, a read transistor, an address transistor, a write transistor, a storage transistor and the following: address bit, read and write, write masking 2.

This memory element is the closest technical solution to the one proposed.

The disadvantage of the known memory element is that it is intended only for operation as part of the operational memory, and performs the function of recording and storing information.

The aim of the invention is to reduce the use of memory memory by t by searching for information based on an arbitrary function of two variables.

The goal is achieved by introducing a second memory transistor into the memory element, the gate of which is connected to the source of the ajqjecHoro transistor, the drain is from the comparison thickness, the source is from one of the polling stations, the source of the first memory tranchestor and the other face of the first capacitor is connected to the interrogation bus .

The drawing shows the circuit element of the first item. The memory element contains the first capacitor - 1; the second one is 2; address transistor - 3; bit bus - 4; Genuine tire - 5; write transistor - 6; readout transistor 7; the first memory transistor - 8; clocking zone 9; comparison bus - 10; the first bus survey - 11; the second memory transistor - 12; the second poll tspshu - 13 and the recording 14.

The memory element works as follows. In search mode 1, a pulse signal is sent to the address bus 5, opening the address transistor 3, and to the discharge bus 4 a signal of logical 1, represented by the potential, which charges the capacitor 2 connected to the gate of the second memory transistor 12 via opened by a signal on the address bus 5, the address transistor 3 to the level of | n logical units. At the same time, the parasitic capacitance of the capacitor is supplied by 10 aneshe sources to logic level 1 in the presence of a pulse on the bus 13 blocking the through current through the transistor 12 during the charging process. In the second clock cycle, the tactical nganu 9 is applied, the opening of the read transistor 7 is opened, and a zero potential is applied to the first interrogation bus 11. In the case of storing 1, the second capacitor 2 is driven through the open reading transistors 7 and the first storage transistor 8 to the level of logic O, the pulse with the threshold 13 is consumed, and the charge on the bus is compared to 10, since the second storage transistor 12 turns out to be closed, which corresponds to the coincidence signal in search 1. In the case of hrs O, the second capacitor 2 and the input of transistor 12 are saved: the potential is logical 1 which ensures the discharge of the parasitic capacitance by comparing 10 to the level of HoriPtecKoro O through the open second memory the transistor 12 after removing the pulse from the bus 13 and corresponds to the mismatch signal when searching 1 e 1.

In the search mode O, in the first cycle and the discharge bus 4, a logical O signal is represented, represented by a zero potential, which discharges the second capacitor 2 to the logic level O through the address transistor 3 to the gate of which a pulse signal is sent, which opens the address gate 3.

In the second cycle, clock pulse 9 is given a pulse, which opens the read transistor 7, and a pulse interrogating the state of the first capacitor 1 is sent to the first interrogation bus 11.

If the first capacitor 1 stores a logical I, that is, is charged; readout transistor 7 is open to the input of the second storage transistor 12, a signal of logical 1 is established, since the second capacitor 2 is charged through the readout transistor 7 and the first storage transistor

the interrogation pulse torus 8, and the comparison bus 10 is discharged to a logic level O through the open second memory transistor 12 after the end of the pulse on the second interrogation bus 13, which corresponds to a mismatch signal when searching for O.

In the case of masking, when searching in the first cycle, the potential O is applied to the discharge threshold 4. The second capacitor 2 is discharged through the address transistor 3, opened by an impulse on the address bar 5, as well as the precharge of the compare 10 bus, onpdca pulse 2 The first scan interval 11 is not applied, which ensures the preservation of the signal O at the input of transistor 12, as well as the potential of logical 1 bus of comparison 10, the corresponding match when searching for O and 1. Thus, the masked mode during the search is different from the search mode a About blocking the interrogation pulse on the first interrogation bus 11 in the second cycle.

Thus, on the gate of the transistor 12, in the search process, the value of the result of the comparison of the information stored in the memory cell with the external information supplied to the associative memory (CAM) for the search operation is established. In the event that all the bits of a word in the CAM coincide with the external word on the gates of the storage transistors 12 of all the memory elements forming the word, a logical level O is set as a result of the comparison in each individual bit. A comparison bus of 10 words, formed by combining the drain of transistors 12, after removing 1 pre-pulse from pre-charge 13, remains charged (in the logical 1 state), since transistors 12 will turn out to be closed. On the comparison string 10, the zero potential will be set only if the information of at least one cell of a given AMU word does not coincide with the corresponding input word length, which is required for the functioning of the ABC.

The operation of the element in reading information is as follows.

Claims (1)

In the first cycle, zero potential is set on the bit bus 4. In the second cycle, control pulses are sent to address bar 5, first interrogation bus 11, clocking bus 9. If the first capacitor stores 1, i.e. is charged, the first memory transistor 8 is open and the discharge bus 4 is charged through open read transistors 7 and the storage transistor 8 polling pulse of the first polling pulse II, which corresponds to reading signal H1PO signal 1. If the first capacitor 1 stores O, i.e. is not charged, then the memory transistor 8 is closed and the discharge bus 4 does not charge, which corresponds to reading the signal O. O. The operation of the element in the information recording mode is as follows: a potential corresponding to the recorded information (O or 1) is established on the discharge bus 4. The recording transistor 6 opens with a pulse through the recording bus 14, which is fed simultaneously with the pulse through the address 5, which provides a galvanic connection for the transistor of the transistor 8 and, the investigator, the first {1 circuit breaker 1 with the discharge bus 4 through the simultaneously open transistor rt) 3 and 6. If there is a galvanic coupling of the capacitor 1 with the discharge bus 4 in the cell,The selected bus 5 will overwrite the corresponding information. In the mode of masking the recording on the recording slot 14, the pulse is not applied and the discharge (charge) of the capacitor 1 does not occur, since the transistor 6 is closed. . The process of regeneration of information in the memory element occurs (in the following way: the first cycle is used to discharge the capacitor 2 through the address transistor 3 by applying a pulse to the bus 5 at zero loss on the discharge chip 4; in the second cycle, the information is read to the second capacitor 2 by supplying pulses on the first interrogation bus and on the clock 9; in the third cycle, a pulse is given to ipscript 14, which opens the write transistor 6, which provides galvanic coupling of the first 1 and second 2 capacitors and the compensation potential due to leakage currents, the proposed memory element, corresponding to the excitation of the second interrogation bus 13, is capable of providing any function of two variables on the comparison bus 10. Indicate: this property allows the parallel coupling of their outputs on the comparison bus, or sequential connection of accumulative elements, natfamer, capacitors, to obtain a general result on | 1, and the actual search for information is based on an arbitrary function of two AC line (equivalence, implication, disjunction, etc.). The memory element for an associative storage device containing storage elements, such as capacitors, one lining of the first capacitor is a switch, the gate of the first storage transistor and the source of the transistor, the gate of the transistor, is connected to the write bus, the drain of the first memory transistor is connected to the source of the transistor read the gate of which is connected to such a shell, the drain of the write transistor is connected to the drain of the read transistor, to the source of the afes transistor and from the second capacitor, the other lining of which is connected to the zero potential bus, the drain of the common transistor is connected to the discharge bus, and the gap to the address bus, compared with the polling, differs in that it has the account of the search for information based on the two functions of the two variables, the second zapomgayuschim transresrr is entered into it, the gate of which is connected to the address flow 1ranz1 {stop, the drain is with equalizing, the source of the first transit traffic Stora n oruga lining with the first capacitor soedieny tstsshoy survey. Sources of information taken into account in the examination of J. US Patent N 1701980, cl. 340-173, 1973.2. U.S. Patent No. 3,876,993, Cl. 340-173, 1975,