SU661465A1 - Degital seismic station - Google Patents

Description

one

The invention relates to the field of seismic prospecting, in particular, to digital seismic stations with a large dynamic range of seismic signal acquisition.

Digital seismic stations are known that contain seismic receivers with preamplifiers, a channel switch, a main amplifier with a digital control factor, containing in turn amplifiers connected in a cascade circuit, keys for switching the gain levels, a logic circuit for selecting the gain factor, a reference voltage source , analogue converter, recording device i.

The disadvantage of these seismic stations is their complexity and. limited accuracy.

In order to realize a given number of gain factors, they require the same number of amplifying cascades & To the latter are high

stability requirements for gain factors, amplitude response linearity and zero drift. Therefore, in seismic stations, for example, the SCR and its foreign analogues, amplifiers are amplified, the cascade gain factors are equal to 4. In this case, the resolution of the analog-to-digital converter is not used, since the signal at its input at any of the amplified coefficient values can lie between the levels JU and D of the scale, i.e. at the 4th, 2th part of the scale.

Analogues with instantaneous readout of the coefficient of ulceration require the use of a large number of comparison devices equal to the number of stages of amplification.

 The closest technical solution is a seismic station containing seismic receivers, channel amplifiers, a channel switch, an amplifier with digital gain control, consisting of cascade-connected amplifiers, for switching and outputs of amplification cascades, a Lostchp circuit for selecting coefficients. analog-to-digital converter and device 2. A disadvantage of the known seismic station is complexity and an error of 5 to accuracy. The difficulty is due to the fact that to implement an amplifier for a given number of gain factors, the same number of gain stages is required. Moreover, the complexity of the logic circuitry increases in proportion to the number of gain factors. The limited accuracy is due to the high demands on the stability amplifiers of the cascade amplification factors, the amplitude response linearity, and the zero value. Changing the threshold of the threshold device, which serves to determine the gain, leads to a discrepancy between the scale of the amplifier and the analog-to-digital converter scale. The gain is set in a few round-tripping cycle. ; At different levels of signals in the channel Lp of some channels, the gain is small and the resolution of the analog-digital converter is not used. The circuit of the proposed invention reduces equipment reduction while improving the measurement accuracy. For this purpose, a digital seismic station contains amplifiers with resistors switched in a feedback circuit, a clock distributor for determining the gain, an OR circuit. moreover, the distributor for determining the gain factors is connected between the cell of the tact of determining the sign and the distributor for the clocks of the analog-digital converter, the outputs for controlling the distributor for the cycles for determining the gain through the circuit. OR are connected to the installation of the bits of the controlled voltage divider of the analog-to-digital converter. The drawing shows the scheme of the proposed digital seismic station, the seismic standard contains seismic receivers 1, key amplifiers 2, comg 3 channel, control unit 4, amplifiers 5 and 6, with resistors switched in the feedback circuit, 8 The output of the title is connected to one input of the reference device o of the device 9 through push-forming and type 10 of the polarity of the sigiap. The other output of the comparing device 9 receives the output of the controlled deposit L1 voltage supplied from the source 12 of the reference power supply. The output signal of the comparison device 9 is supplied to the controlled voltage dividers 11, the polarity control logic control circuit 13 and the key control logic 14, the sequence of ticks for determining the sign, the gain and the digital-analogue conversion, is determined by the symbol of the 16 tick distributor Determining the coefficients of the amplification and distributor - 17 clocks of analog-digital conversion. The output of the distributor, 16 clocks of determining the gain, through the circuit OR 18, is connected to the input of the installation of the bits of the control divider 11 of the voltage of the analog-to-digital conversion. The code of the sign, coding gain and the anapogram digital conversion code is fed to the registering device 19 with the logic circuit 13 controlling the polarity converter, the key logic circuit 14 and the controlled analog voltage digital converter 11. The proposed device works as follows. Before connecting the corresponding channel to the input of the amplifier 5, the signal from the control unit 4 sets the controlled voltage divider 11, the logic converter control logic 13 and the key control logic 14 to the zero state. The resistors 7 switched in the negative feedback circuit of the amplification amplifier 5 are made so that when the switch 8 is closed, the gain of the amplifier 5 is 1, and when the switch 82 is closed, the gain is equal to 16. With the switches of 8 8 closed and 8 the gain of amplifier 6 equal to 1, 2, 4 or 8, respectively. Key coding and code-corresponding gain factors K5 and K l of amplifiers 5 and 6 are given in the table

Claims (2)

a: -G ::; ::;one ::.::.-. A logic 13 control circuit for converting the voltage, a logic circuit 14 for controlling the keys and a controlled voltage sharing 11 together with the cell 15 of the sign detection cycle, distributor 16 cycles for determining the coefficient of the amplification and distributor 17 cycles for the analog-to-digital converter perform the algorithm pozr pozhn balancing. After setting zero, the output voltage of the controlled voltage divider 11 supplied to the input of the comparison circuit 9 is equal to O. The gain with the zero code of the key management logic circuit 14 (see table) is maximal. A start pulse, which arrives at the input of the sign of the 15th clock of the character detection from the control unit 4, starts the clock distributor. The output signal of the sign definition cycle 15 affects the control logic 13 of the polarity converter, setting it to a state in which the polarity converter 10 transmits the output signal of the amplifier 6 to the input of the comparison circuit 9 without polarity inversion. After a voltage transient setting, the output signal of the circuit 9 of the voltage depends on the polarity of the input signal. The next clock cycle is determined by the presence of a signal at the first output of the distributor. 16 clock cycles for determining the gain. The falling edge of the signal of the decoding cell 15 according to the output signal of the comparison circuit 9 sets the control logic 13 of the polarity converter to a state in which the output signal of the converter is 10 polarity one polarity with the voltage of the polarizer 11c. State of logic -. The control polarity circuit 13 determines the sign of the input signal. The output signal at the first output of the distributor, 16 cycles of determining the gain, sets in the logic control circuit 14 of the chips a 1OO code pattern, which corresponds to a gain of 8 (see table). At the same time, the output signal from the first output of the distributor, 16 cycles of determination of the gain factors, through the OR circuit, sets the controlled voltage divider 11 to one of the two code combinations: O ... 01 ... 11. In a controllable voltage divider with weights of binary code bits, the specified code sequence corresponds to an output voltage equal to half the low-order bit of the analog-digital converter scale. After a voltage transient setting, the output signal of the comparison circuit 9 determines whether the output signal of amplifier 6 is greater or metasc, when the gain of amplifiers 5 and 6 is equal to 8, is half the analog-to-digital converter scale. The second cycle for determining the gain is set by the voltage at the second output of the distributor 16 of the clock for determining the gain, which sets the unit in the second code bit of the key control circuit 14 and holds the previous code pattern in the controlled voltage divider 17. The trailing edge of the output of the first cycle, depending on the value of the output signal of the comparison circuit, resets the first codeword to the zero state or leaves it in. unit state, the first bit of the gain code is defined. In logical cxfeMe 14 key management, one of the code combinations 010 or 110 is set, which corresponds to a gain of 32 or 2 (see table. At the moment of the transition to the third cycle about the result of comparing the output signal of amplifier 6 with a voltage corresponding to half the scale of One of the four gain factors is set in the digital converter, which is determined by the bit code of the gain code. At the moment of transition to the fourth clock, which is determined by the presence of signals at the first output of the distributor, 17 clock cycles - digital converter, the third digit of the code of the amplification is determined. The signal from the output of the OR circuit to the controlled voltage divider 11 is terminated. When moving to the fifth cycle, the first digit of the analog-to-digital converter is detected, etc. 1 4. The gain is determined from the condition in which the output signal of the amplifiers always has a value from the maximum voltage range to the maximum voltage, which will fully realize its resolution robnost. The use of two amplifiers with a set of gain factors 1 and 2 for one AND 1, 2; 2, 2 for the other allows to expand the dynamic range by 42 dB Three amplifiers with gain factors 1 and 2® for one 1 and 2 for the other and 1 2, 2, 2 for the third, providing 16 binary gain factors and allowing the dynamic range to be extended by 90db, etc. The output of the comparison circuit provides a serial code, the first bit of which is significant, followed by bits of the gain and bit codes of the analog-to-digital conversion. The proposed device greatly simplifies the seismic station while simultaneously ensuring a high accuracy of the analog-to-digital converter, since a controlled voltage divider and a comparison circuit of the analog-to-digital converter are used to determine the gain code. When the input of circuit 5 is closed on the body of a closed circuit comparison circuit, it is determined: there is a care zero of amplifiers and a comparison ampli fi er that makes it easy to grab the entire path of the automatic adjustment of the wob. 6 65c. The speed is determined mainly by the type of operating instrument used. The time required to establish the output voltage of modern operating circuits is about the same as that of the comparison circuit and the control of this voltage divider, which also uses operational amplifiers. The 153 series microcircuits, which have relatively low speed, ensure the conversion speed up to 1% of IT / sec. The proposed station has passed laboratory and field tests, used in autonomous marine buoy seismic stations. DETAILED DESCRIPTION OF THE INVENTION A digital seismic station comprising seismic receivers, channel amplifiers, a channel switch, cascaded amplifiers, keys, a key control logic for selecting gain factors, an analog-to-digital converter, and a recording device are distinguished by the fact that, in order to reduce equipment with one FMpeHI to increase the accuracy of the measurement, it contains amplifiers with commutated resistors in the feedback circuit, a clock distributor, gain determinations, an IL circuit , The distributor bars determining gain factors included mezkdu cell cycle and determining the sign raspredepitelem cycles analog-digital converter, the control outputs of the distributor strokes determining kreffitsienta gain through an OR gate connected to the set input bits controllable voltage divider analog-to-digital converter. Sources of information taken into account in the examination 1, Polshkov MK Theory of analog and digital seismic equipment, M., Nedra, 1973, 2. Forward Germany No. 1906196, cl. 42c, 42, 1973.