SU660271A1 - Frequency divider - Google Patents

Description

(54) FREQUENCY DIVER

The invention is intended for use in pulsed technology, especially in devices that require a large business ratio. NIN with high stability, for example, in sync generators of television installations, in calibration devices for measuring radar stations and other devices in which synchronization of relaxation generators is performed by repetition rate. With this, as a synchronizing oscillation, the harmonic oscillation with a frequency from 20 Hz to 80 kHz can also be applied without converting it into an impulse. Known frequency dividers made on blocking oscillators. (, 2. The first of the known devices contains three transistors, two capacitors and three pulse transformers 1. However, this frequency divider n provides a large and stable division factor. The second of the known devices holds the blocking generator is on a crisis, the resistor, the discharge transistor, is connected in a circuit with a common base, and the time sets the capacitor 2. This frequency divider has the following disadvantages: first, the time setting the capacitor included in the reverse circuit During the blocking process, a small base current is charged, therefore the charge (voltage) at the time of the master capacitor will be small, which does not provide a large division factor with high stability and, secondly, during pauses Between the charge, the time of the driving capacitor runs a constant reverse base current through the base circuit of the transistor, which discharges the time of the driving capacitor, which does not allow the voltage of the driving capacitor to remain constant during the pauses between the external sync pulses. ization, sledovate.G1no reduces the dividing factor and its stability. The purpose of the invention is to increase the division ratio while maintaining stability. The goal is achieved by the fact that in a frequency divider containing a transistor blinking oscillator, the common-base discharge transistor is connected to the common base, the time specifies the capacitor, one plate is connected to the emitter of the blocking oscillator transistor and the discharge transistor collector, and the other facing - to the base of the latter.

The drawing shows a circuit diagram of the proposed frequency divider.

The frequency divider contains a blocking generator made on a 1 pnp type transistor with a transformer positive feedback and a 2 pnp type discharge transistor connected according to a common base circuit. The blocking generator has a pulse transformer 3, a filter 4, a negative voltage surge shunting circuit 5 (diode and damping resistor), a high-resistance resistor b used to supply positive bias to the base of transistor 1 and a time setting capacitor 7 connected to the emitter circuit of transistor 1. At the input of the discharge transistor 2, the dividing circuit RC is switched on.

The frequency divider works as follows.

When the power supply is turned on, the blocking generator is triggered and the time of the driving capacitor 7 is discharged To the maximum voltage that is applied to the base of transistor 1 through the winding of the feedback transformer 3 and closes the transistor 1 until the full discharge time of the driving capacitor 7. At the same time This transistor 2 is closed in its initial state. When the first (and subsequent) negative pulse or the first negative half-period of harmonic oscillation from the source of oscillations, whose frequency is to be divided, arrives at the input U, gx, transistor 2 opens for the duration of this pulse and the drive capacitor 7 is quickly discharged by a certain amount, image step tension. Step size quantized

determined by the amplitude and duration of the input pulse. If the frequency, amplitude and duration of the external synchronization input pulses are constant, then the magnitude of the steps and the length of time between adjacent quantization steps will be constant and a linearly decreasing positive voltage will be generated for the duration of the driving capacitor 7.

With discharge, the time of the setting capacitor is 7 pth pulse to zero

the blocking generator is triggered, a pulse is generated at the output of Ugbix as a result of the effect of a frequency divider n input pulses at the input UBX,

and the time setting capacitor 7 is charged again until Vffjtanc, then the process repeats.

Thus, the output is a pulse with a frequency of the sequence fj ,, fbx / M (rD fax is the pulse frequency or harmonic frequency applied to the input UBX / to be divided; n is the division factor).

Claims (2)

Invention Formula A frequency divider containing a blocking oscillator on a transistor, a discharge transistor connected according to a common base circuit, and a stitching capacitor time, characterized in that, in order to increase the division ratio while maintaining stability, one plate of the master capacitor is connected to the emitter of the transistor blocking -generator and the collector of the discharge transistor, and the other lining - to the base of the latter. Sources of information taken into account in the examination 1V USSR Author's Certificate No. 146347, cl. And 03 K 25/08, 1969. 2. Glebov B.A. Blocking transistors, M., Energie, 1972, p.97, fig. 4-4b. . VSi ,,