SU649156A1 - Discrete information receiver - Google Patents

Description

To increase the accuracy of reception, a comparator 6, an additional valve 7, a major block 8 and a series-connected coincidence block 9 and a accumulator block 10, the output of which is connected to the first input of the majority block 8, the first output of which is connected to the first output of the comparator 6 and the control input of the additional valve are entered 7, the output of which is connected to the control input of the clanan 4 and the first input of the coincidence unit 9, the second input of which is connected to the output of the accumulator 3, the second input of the majority block 8 and the first input of the comparator ora 6, the second and third inputs of which are connected respectively to the outputs of the decoder 2 and analyzer error 1, the second output of the comparator 6 is connected to the third input of the majority block 8, the fourth input of which is connected to the output of the decoder 2, and the first and second outputs of the majority block 8 are connected accordingly to the control input of the valve 4 and the input of the receiver 5, while the output of the error analyzer 1 is connected to the signal input of the additional valve 7.

The device works as follows.

The signal goes simultaneously to error analyzer 1 and decoder 2. From the output of decoder 2, the information part of the code block in the original code is written to accumulator 3. If analyzer 1 did not detect an error in the code block, it allows information output from accumulator 3 through valve 4 to receiver 5 If analyzer 1 detects an error in the code block, it issues a "Reshoot" signal that prohibits the passage of information from accumulator 3 through valve 4 to receiver 5 and allows overwriting of this information through coincidence block 9 to accumulator 10 firs.

Information from accumulator 3 is also fed to comparator 6, to the other input of which simultaneously signals of the information part are sent repeatedly via the signal "Rescan of a code block received with an error during the first transmission. If at the repeated reception of this code block the error is not detected, the output of information from the accumulator 3 to the receiver 5 is permitted, as during the first transmission. Otherwise, the comparator 6 outputs the corresponding signal from analyzer 1, according to which the comparator 6 produces the result of comparing the information part of the code block, received for the first time and again.

If they match (i.e., the information parts are not distorted), the output of the blocking signal from the analyzer 1 through the additional valve 7 is prohibited by the signal from the comparator 6, and the information from the accumulator 3 is output to the receiver 5. Otherwise, the signal "Responsive , the third transmission of this code block occurs, the information from accumulator 3 is compared with the incoming information from decoder 2 in the manner described, at the same time information from accumulator 3, block of accumulators 10 and decoder 2 is fed to the majority block 8, where Odita error correction (symbol groups by, for example, wire marks, or across the code block). If the information parts of the code block of the second and third transmissions do not match, the signal from comparator 6 gives the major block 8 the result of error correction 5 to valves 4 and 7. If errors are corrected, the output of the signal from analyzer 1 through valve 7 and output of information from accumulator 3 through valve 4 is prohibited, and majority block 8 provides corrected information to information receiver 5. If errors are not corrected (uncertainty), the output of the Signal Rescan from Analyzer 1 signal is permitted, and the output of information from drive 3 to receiver 5 is prohibited. 5 In the fourth transfer, the comparator’s information parts of the third and fourth transmission code blocks are compared, and in the majority block - correction of errors on the second, third and fourth gear. The information transmitted the first time is erased. Further work is carried out in a similar way before receiving information without errors or before correcting errors.

If it is necessary to strictly limit the number of repetitions of the same code block, the majority block is designed so that there is no uncertainty in error correction (for example, by comparison of groups of characters).

The number of code blocks for which majority comparison and error correction takes place is chosen based on the permissible loss of reliability of the information.

Thus, the proposed device allows to increase the rate of transfer of discrete information and reduce the number of repetitions of the same code block in hardware with a decisive feedback.

Claims (1)

1. Purtov LP and other Elements of the theory of data transfer. Channels. Systems L., VKAZ, 1968, p. 143.