SU645151A1 - Binary-decimal-to-binary code converter - Google Patents

Description

/ H-1

the new adder is composed of

-2 oneIg2

Binary Binary with Shmators and Nolumummators. .

The invention is illustrated in the drawing, which shows a converter and bit binary decimal codes for .-::.: .-.

The device contains tetrads of input inputs Y-4, binary one-bit, summers 5–7, half-summers 8–9, and the element OR: 10, which constitute a multi-digit combinational adder L; binary one-bit adders 12-17, half-adders 1 / 5-1 9 and element. OR 20, the coordinates constitute the multi-digit combinational adder 21; binary one-bit adders 22-30, half-adders 31-5 "3, which constitute a multi-bit combinational adder 34, elements .OR 35-37, as well as output poles 38.- - - -,.; ....--. -v, -..-: - ,, r-, -: .-:

The first, second, third, fourth input poles of the tetrad / (the count is kept from left to right) are connected appropriately to the elements 10 and 5, 8 and 6, 5 and 7, 6 and 9 of the multi-digit combinational adder, //.

The first input poles of tetrads 2, 3, 4 are connected respectively to one input element OR 35, 3-6, 37, the other inputs of which connect the connections respectively to the outputs of the one-digit adders / f7, 30, and the outputs of the OR circuit, respectively, to the inputs of elements 6, 16, 29. The second / and third bits of tetrads 2, 3, 4 connect Hbj; respectively, to elements 7 and I / 7 and 19, 30 and 33. (Each i-th output of multi-digit combinational adders //, 21 are connected respectively to the / -th and (t-2) -th inputs of combinational adders 21, 34. The outputs of the adder 34 are connected to the output buses 38 of the device.

Older bits of the multiply combinational combiners adders // and 2 / are made in the form of OR elements.

The device works as follows. On notebook i / -4 input poles, a set of single and zero signals is generated — a number code, for example, 10011001100Н001.

The inputs of binary one-bit adders and half-adders 5-9 and the element OR 10, which constitute the multi-digit combinational adder, // receive the code rOQliOOl through the tetrads of the input poles I / and 2. At the adder // the Bicex codes are added:

1) code entering through the input poles of the tetrad, 2; ,

2) the code entering through the input poles of the tetrad / and shifted from the previous one by one bit to the left;

3) the code arriving through the input sections of the tetrad / and shifted relative to the previous one by two bits to the left

-f 1001 1001 1001

llOOOIl

At the output of the adder /, /, the code 1100011 appears. This code and the code 1001, applied to the input poles of tetrad 3, are fed to the inputs of one-bit adders and half-adders, / i5-i / .9 and the OR element 20 adder 21. At this adder there is a summation of three codes:

1) the code entering through the input band of the tetrad 3 ;,

2) the code, which is from the output of the adder / I / and shifted one bit to the left relative to the previous one;

3) the code coming from the output of the adder // and shifted by two bits relative to the previous one.

+1001

POOOM 1100011

lllllOOlM

At the output of the adder 311, the code lllllOOllil appears. The outputs of the binary adders and half adders 22-33 constituting the multi-digit adder 34 are fed through the input poles of tetrad 4, the code 1001, and from the output of the adder 21, llMliOOlU. Adder 34 occurs

addition of three codes:

1) the code coming through the input tires of the tetrad 4;

2) the code coming from the output of the adder 2il and shifted from the previous one by one bit to the left;

3) the code coming from the output of the adder 21 and shifted relative to the previous one by two bits to the left:. + 1001

1111100111

11,11100111

10011 yuZHGG

On the upstream of the adder 34, the code 100.1 appears llOOOO111, which is binary

equivalent of a binary-decimal code (1001,10.01.1001.1001) 10. Thus, the proposed device realizes the conversion of a binary-decimal number into a binary one.

In the proposed device, the number of one-bit adders and half-adders constituting parallel multirases -1 /

y / flfi

-2

Ulg2

full adders equal

where / is the number of a multi-bit combinational adder, n is the number of binary-ten bits, a (i & the closest integer, but such that, At the closest