SU627543A1 - Permanent storage - Google Patents

Description

The invention relates to automation and fast computing technology and can be used in digital computers.

Known constant memory

arrangement, containing a numeric block with the number of communication elements 1.

It is characterized by high power consumption, even load on address buses.

Most by. The technical essence of the invention is a persistent storage device, a hollow address decoder, the outputs of which are connected to the accumulator inputs, and control buses, which are connected to the adders but module two C2J.

The drawbacks of the device are a large number of communication elements, which means that the size of a numerical block is low, the reliability of operation is low.

The purpose of the invention is to increase the reliability as well as reduce the power consumption.

The goal is achieved by the fact that the read-only memory contains a register, additional control buses, one of which is connected to the additional modulo two matrices via elements And, connected through two modulo additional modulators, with the corresponding elements And with the inputs of the main and additional adders modulo two ,. and the inputs are connected to the outputs of the register.

The drawing shows the functional scheme of the device.

The device contains an address decoder 1, a drive 2 and a correction block 3, built on the basis of modulo two adders, register 4 and AND 5 elements. Drive 2 contains discharge buses 6, control buses 7 and additional bus 8 controls. Outputs of address decoder 1 connected to the inputs of the drive 2. Additional control bus 8 through a group of elements And 5 connected to the first inputs of additional modulators two 10, the second inputs of which are connected to the corresponding control bus 7. Discharge buses of the drive 2 connectors to the inputs of the main adders modulo two 11, the outputs of the additional modulators are two 1O connected through element 5 and the corresponding inputs of the main modulators two 11. The outputs of register 4 are connected through the corresponding elements I to the inputs of the main 11 and additional 1O matrices modulo two. Pre-transformed raw information is written to drive 2. Original information is pre-transformed to reduce the number of ones, i.e. the numbers of communication elements are as follows. The bits of the codes of the recorded numbers are divided by K, the groups and, if the number of ones in this group of bits is greater

0001

01101

About About OOO1

O1O1

0101 0001 Transf. code O101 O O The values of the transformed bits to numbers are recorded in the communication elements of accumulator 2. In practice, in the matrix of accumulator 2 after manufacturing, there are failures that can be of the type GENERATOR O (zero defect) or GENERATOR 1 (single defect). A zero defect occurs if the direction of the defect that has arisen and the direction of the recorded information are the same (i.e., we have the GENERATOR 1 defects, and the record is 1), and a single defect with different directions of the failure and the recorded bit. If in places where it is necessary to write the bit of this group for the majority of numbers a combination of zero and leading defects has arisen, it is possible to make such a switch in correction block 3 so that these defects are masked. This takes place with group failures in the matrix of accumulator 2. For example, for numbers (K 2.) in the storage elements, where it is necessary to record 1-L and 3rd-bit, there are single defects, and where 2-L bit e is zero defects.

2 E1

33

E2

E1

0111

1111

ABOUT

0000 1 1000

one

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Claims (2)

about 0.5 / P- (- bit length of the numbers to be written), then the reverse code of the group is written, and the unit is written to the appropriate control elements of the communication of this group. If in the code of this group of bits the unit number is less than O, 5, then the code does not change, and O is written to the control elements of this group. After performing this operation, a similar transformation of the codes recorded in the control elements of the first group is performed. The codes of these digits are divided into K 2 groups. And if the number of units in a given group is greater than 0, 5 t, (), the digits of this group are inverted, the additional group element of the second group is recorded 1, and so on. It lists the sequence of operations for transforming a number with the code 101000111110111 provided that 4, K 2, K 1. Example. О О ОООО О 10ОО О There are no defects in the memory elements in which the remaining bits of this group are recorded. To mask these faults, it is necessary to invert the values of the 1st and 3rd bits of the groups and leave them unchanged for the 2nd digit. The values of all the remaining bits must also be inverted and, accordingly, written into the additional control element of the communication of the first group. However, when reading, the additional control element of the first group is blocked for the 2nd bit using the elements of AND 5 and register 4. Thus, the persistent storage device disguises the defects of the storage matrix, the multiplicity of which lies in the interval j h-. For example, when P 16, Kp 1 in the 21-phase matrix of the accumulator, 95.2% of all possible single failures are masked, 84.3% are doubled, 66.5% are triple, 48.3% are fourfold, 31.8% are ticrates, etc. DETAILED DESCRIPTION OF THE INVENTION A permanent storage device comprising an address decoder, the outputs of which are connected to the drive inputs and control buses connected to modulators two, characterized in that, in order to improve the reliability of the device, it contains two modulators in the register , the AND element for each adder and additional control igans, the latter of which are connected to the additional modulo two adders via the And elements, the others are connected through additional adders for the module two with corresponding elements AND, the outputs of which are connected to the inputs of the main and additional adders, modulo two, and the inputs are connected to the outputs of the register. Sources of information taken into account in the examination; 1, USSR Author's Certificate NO 376808, cl. Q 11 C 17 / OO, 11.71. 2. Memory devices. Under the RVD, Krayzmera LP M, ,, Energie, 1974, p. 89, fig. 5.6.