SU624244A1 - Pulse frequency signal differentiator - Google Patents

Description

The invention relates to the field of automation and computer technology and can be used, in particular, for digitally measuring measured frequency-pulse signals.

A device for differentiating pulse frequency signals is known, comprising a cube raising unit, a period difference separating unit, an And element, and a counter fl.

The disadvantage of the device is the reduced accuracy of differentiation.

It is also known a device containing a control unit, a reference frequency generator, a controlled frequency divider, an instant frequency frequency meter, a period meter, pulse counters, elements and groups of elements AND, OR 2.

The disadvantages of this device are the complexity of the constructive implementation and the reduced accuracy of differentiation.

The prototype of the invention is a device for differentiating frequency pulse signals comprising a control unit connected by an input to an input

device, the reference frequency generator, the output of which is connected to the signal input of the first controlled frequency divider and is connected via an uncontrolled frequency divider to the counting input of a period counter connected by bit outputs to the first inputs of the AND elements of the first group connected by outputs to the control inputs of the first and the second controllable frequency dividers, and the control inputs of the third controllable frequency divider are connected to the outputs of the elements AND of the second group, and the zeroing inputs of the period counter and the control Frequency dividers, second inputs of elements of the first group and first inputs of elements of the second group are connected to the corresponding outputs of the HzT control unit. The disadvantages of the prototype are the complexity of the design and reduced performance in generating a digital derivative code, due to the need to introduce a digital frequency meter to convert the output signal device. The purpose of the invention is to simplify the device and increase the speed when forming a digital derivative code. The goal is achieved by adding a result counter to the device, an element I and a period requisition unit connected by an input to the device input, and an output to the first input of an additional element I connected by an output to the input of a result counter n connected by the second input to the third controlled frequency divider, the signal input of which is connected to the first output of the second controlled frequency divider connected by the second outputs to the second inputs of the elements of the second group and connected ignalnym input to an output of the first councils l emogo frequency divider. The invention is illustrated in the drawing, which shows a block diagram of a device. The device contains a control unit 1, 6rtOK increments of period 2, element 3, result counter 4, reference frequency generator 5, uncontrolled frequency divider 6, controlled frequency dividers 7, 8, 9, period counter 10 and two groups of elements 11 and 11 12. Managed frequency dividers 7, 8, 9, as well as in the device prototype, can be performed on pulse counters, memory registers and groups of elements AND transfer. The device works as follows. The input pulse frequency signal f / is fed to the input of the increment block of the period at the output of which the increment signals of the input signal period are formed, and to the input of the control unit that controls the operation of the period counting 1O, frequency dividers 7, 8, 9 and groups of elements And 11, 12. The pulses of the reference frequency f o from the output of the generator of the reference frequency 5 are fed to the input of the controlled frequency divider 7, where they are divided by the number entered from the period counter 10 through the group A 11. At the outputs of the period counter 10, a code is generated N., proportional ny expired input period. This shad is formed by filling the selected period T with the pulses of the reference frequency p divided by frequency divider 0 by a constant number k. After each input pulse arrives at the input of the control unit 13, this unit ({controls the following control / s) the inputs of the control unit 13 of the controlled frequency divider 8, which are outputs of the memory register of this divider, through the group of elements And 12, the code C |. of the previous period is transferred to the memory meter of the frequency divider 9, then the reset is performed Isters of memory in frequency dividers 7 and 8 and they record FROM a period counter 10 through a group of elements AND 11. The value of the code of the elapsed period.After this period counter 10 is nullified, and a new measurement cycle of the next period begins The output of frequency divider 7 forms a frequency N, -. V which is divided in the frequency divider 8 by the number NJY. On the nej®oM output 14 of the frequency divider 8, a frequency is formed Frequency f in the frequency divider Frequently, on the output of divider 9 by the number frequency 9, the frequency -f -f IT -il- l Output frequency pulses from frequency divider 9 t through the element And 3, opened by block 2 for a time equal to the increment of the period DT, to the counting input of the result counter 4, where they are summed. After the end of the measurement cycle, at the outputs of the bits of the counter 4, the code K df, VIft- -1 N 1 AT -s- OUT 3 1 is formed | at is the proportional first derivative of the input frequency in the elapsed period. The sign of the derivative Sicfn f. Determined in block 2 by the sign of the increment of the period Formula of the invention A device for differentiating pulsed segneaths containing a control unit whose input is the device's inputs, a frequency generator, the output of which is connected to the signal-i input of the first controlled frequency divider and through unsupervised The splittable frequency divider is connected to the counting input of a period counter, - connected by bit outputs to the first inputs of the AND elements of the first group, connected by outputs to the control inputs of the first and volts the controlled inputs of the third controlled frequency divider are connected to the outputs of elements AND of the second group, with the inputs for zeroing the period counter and the controlled frequency dividers, the second inputs of elements AND of the first group and the first inputs of elements AND of the second group are connected to the corresponding outputs of the control unit, characterized in that, in order to simplify and increase the speed in the formation of the digital derivative code, a result counter is additionally introduced in it, the element AND and the block Period, connected to the input of the device, and the output to the first input of an additional element And connected by an output to the input of the result counter and connected by the second input to the output of the third controlled frequency divider, the signal input of which is connected to the first output of the second controlled frequency divider connected by the second outputs to the second inputs of the elements of the second group and connected by a signal input to the output of the first controlled frequency divider. Sources of information taken into account during the examination: 1. USSR author's certificate M "399860, cl. Q About F 7/38, 1971. 2. Order No. 2119484 / 18-24, cl. Q 06 Q 7/18, 1975, according to which a decision was made to extend the author's certificate. 3. Forward number 2358616 / 18-24, cl. Q 06 Q 7/18, 1976, according to which a decision was made to extend the author's certificate.