SU618796A1 - Storage cell - Google Patents

Description

(54) MEMORY CELL

I

The invention relates to computing and can be applied to input devices and memory buffer devices.

The memory cell is known, the ngitrimer is a trigger on two elements NOT, the elements AND and OR l.

The closest technical concept to the invention is a memory cell, containing two series-connected OR elements — NOT, three keys and a transistor. The first input of the first element OR is NOT connected via the first key to the cell input, the second input of the first element OR NOT connected via the second key to the output of the second element OR NOT, and the transistor is connected between the power supply and the output bus of the register 2.

A disadvantage of this device is the presence of a direct connection between the keys, i.e. strict requirements for the ratio of the durations of the control and information signals; the absence of the possibility of correcting the output information without destroying information in the memory.

The aim of the invention is to expand the field of use of the cell by increasing the range of control signals.

The goal is achieved by the fact that the proposed cell contains two additional keys, the output of the second element OR NOT through the first and second additional keys is connected to the output of the cell, and the point of connection of the additional keys through the third key is connected to the power bus.

FIG. .1 is a finite memory cell diagram; in fig. 2 - cxeNU variant of memory cells on field-effect transistors.

The Ps1m-ty cell contains the first 1 and second 2 elements OR-NOT, the first 3, the second 4 and the third 5 keys, as well as the first 6 and second 7 additional keys.

The key 3 is connected to the input 8 of the cell, the key 7 to its output 9, and the key 5 to the power bus 10. The additional inputs 11-15 of the cell serve to set various modes of its operation.

When the memory cell is executed on field-effect transistors (FIG. 2), the first element OR-NOT 1 contains three field-effect transistors, and the second element OR-NOT 2 contains two field-effect transistors. An auxiliary key of the central bank can be connected to the memory cell, which provides auxiliary modes of operation.

The elements are OR-NOT 1 and 2 and the key 4 is TiHtrrep, in which the duration of the input signal depends only on the value of the feedback circuit.

The auxiliary switch 16 provides for setting the trigger to the zero state, since the recording signal and the control of 10 DCM input of the patch 3 interrupts the feedback circuit (which contributes to the shortening of the recording time zero TG). reduction of the discharge time of the quiveite capacitance of the load circuit.

An information signal, for example, from the operator’s console (not shown) is fed to the input of patch 5. Key 6 determines what information is sent to the output of the cell, if key 6 is closed, information on the correction circuit (clot 5) is output, if When the cell is open, the output of the cell receives information with a trigger depending on the availability of corrective information. Key 7 allows the information to be received from the cell.

The memory cell works in the following way.

The control signal is input to the input 14 3 and briefly the input of the key 16. The trigger input is disconnected, and the feedback circuit is briefly interrupted, and a logical zero (input 8) is set or saved at the Output Trigger. The feedback circuit of the trigger is closed when there is a logical unit at the input of the key 4. When a logical unit arrives at the input of the First Element OR NOT-1, the trigger is set to one, which is set as the key 4 is open,

If key 6 is OTL (input unit) information from the trigger enters the output circuit of the cell (key 7), if the key is 6 closed, the output circuit of the cell enters zero or one unit of the correction circuit through key 5. The information in the trigger can be

changed only with the new input of the control signal at input 14 (feedback circuit razvvvm).

If key 4 is closed (zero at its input), if there is a control signal at input 14, the unit at the output of the flip-flop remains until the end of the signal of the unit at input 8 of key 3 or until the end of the control signal at input 14. With the help of key 7 of choice, cell receiver information.

The proposed cell structure allows you to create devices for various purposes with low requirements for synchronization, duration, shape and amplitude of signals arriving at it, having different control methods / low requirements for cable communication lines.

Claims (1)

1. USSR author's certificate 367555, cl. I 03 K 21/00, 03/12/73. 2 USSR author's certificate 395904 ,, CL QH C 19/28, 08.01.74. 8 3 L.  f, 1 7 .Л9 ta g