SU610098A1 - Device for preparing data for input to computer - Google Patents

Description

one

The invention relates to the field of computing. It can be used in the construction of data preparation devices obtained during tests and studies of complex objects for processing on electronic computing machines (computers) - in automated data processing systems.

The peculiarities of the data obtained by testing H tests of complex objects include relatively high arrival rates, interference and the incompatibility of their structure and formats with those adopted in a computer. Devices for preparing data for processing on a computer (1), {2, are known, comprising a data input unit, a format conversion unit, a buffer memory, an external memory, a control unit, and an error correction circuit.

A preparation device and others () allows you to generate data (using the keypad), place it in predefined formats and transfer it to an external memory card. To confirm the collected data before they are stored in the buffer memory, the data are completely presented to the operator for visual inspection and manually corrected errors, i.e., a correct correction of incorrectly typed characters is made. Pe2

The data prepared in the specified format starts after the command is given by hand.

The device management, detection and correction of errors the operator manually leads, which 5 reduces the bandwidth of the device. In addition, only meaningful error correction is carried out in the device.

Device 2} also includes a sign correction circuit that allows you to carry out 1 substantive correction of the recorded character manually (for example, if instead of the symbol A, the operator mistakenly entered the symbol B in the device and this error was detected, then the operator turns on the sign correction circuit, erases the false symbol and writes in its place is the correct symbol), as well as the block correction scheme. The latter serves to modify a block of data already transferred to the buffer memory. In this case, the operator erases the data block, located in the buffer memory, without overwriting the external memory in order to write to the buffer memory a new (corrected) data block.

The bandwidth of the device is due to the fact that the error is corrected manually, as well as the fact that only one block of buffer memory is applied (until

while lUc the contents of this block will not be copied to an external memory, writing to it is impossible). In addition, only meaningful correction of faults is carried out in this device.

The closest in technical essence to the invention is a device comprising a data input unit, a communication unit and a format conversion unit, two buffer memory units, interface units, an external memory and a control unit. The information output of the data input unit is connected to the first input of the communication unit and format conversion, the two outputs of which are connected respectively to the inputs of the buffer storage units, the outputs of which are connected to the input of the external memory unit through the interface unit. The outputs of the control unit are connected respectively to the control inputs of the input data, interface, external memory unit.

The device works as follows.

The data bytes come from an input unit to a communication unit and a format conversion that packs them into predefined formats (words) and transmits these words to one of the buffer memory blocks. The second block of buffer memory is in idle mode at the initial moment. After the last cell of the first block of the buffer memory is filled, its output is connected to the input of the external memory block, and its contents are copied to the external memory block, and the data from the input block through the & The zi and format conversions fill the second block of buffer memory at this time. After the last cell of the second block of the buffer memory is filled, a similar process takes place, i.e., the data from the second block of the buffer memory begin to be copied to the external memory block, and the first block starts to be filled again.

Thus, due to the push-pull mode of operation, the capacity of the device is limited only by the speed of the memory block (buffer or external).

The disadvantage of the device is its low efficiency in the preparation of multi-channel measurement data having a frame structure and registered under interference conditions due to the complexity of the sorting programs and, consequently, the large amount of computer time spent on sorting such data. Due to the fact that the paths of the direct and inverse transformation of information (recording and reproduction) introduce various kinds of interference, reliable values of the measured parameters and service symbols arrive at the input of the preparation-data device with an admixture of disturbances (malfunctions). At the same time, there are failures of a substantive nature, i.e., distortions of the physical values of the measured parameters. The most dangerous for the data preparation device are faults related to clock pulses, i.e., the disappearance of one or several clock pulses within the frame, the occurrence of clock pulses of one or several noise pulses (spurious clock pulses) on the track.

Suppose that the number of channels in a frame is 32, the number of bytes in word 4, the capacity of a block of buffer memory is 4096 words, 512 frames are placed in one memory block. In normal operation (without failures), the measurements of the first channel are located in the first sector 1, 9, 17, 25 ... 4089 cells of the buffer memory blocks. Thus, to obtain the entire sequence of measurements related to a particular channel, it is sufficient to revert to the specified addresses. In addition, the addresses of consecutive measurements of a given channel are the same in each recording file on the external memory block (invariants with respect to the file number), since each file contains an integer number of frames.

Suppose now that the sync pulse corresponding to the first dimension of the second channel has disappeared.

In this case, the first dimension of the first channel will be recorded in the first sector of the first word, the first dimension of the third channel (and not the second, as in normal operation) will be recorded in the second sector, measurements of the fourth channel will be recorded in the third sector, and so on. This means that one sector is shifted to the left and the last word is not formed by the arrival of the end-of-frame impulse, that is, 7 words were output in the frame, not 8 words.

A similar picture is obtained when false sync pulses appear, with the difference that the shift occurs to the right.

Thus, in the presence of failures, the unambiguous cooTBetcTBHe between the address and the channel number in the memory block is violated. In addition, each file in the external memory block does not contain an integer number of frames, i .e. The invariance of the addresses of successive measurements of specified channels with respect to the file number is removed. This leads to a significant complexity of sorting programs and, accordingly, to a large expenditure of computer time for sorting data.

The aim of the invention is to increase the efficiency of the device by simplifying the sorting programs and reducing the cost of computer time.

The goal is achieved by introducing a key and a frame structure recovery unit into the proposed device, three inputs of which are connected respectively to the first output of the data input unit, the third output of the communication unit and format conversion and the output of the control unit, the first output to the second input of the link unit zi and format conversions, the second output is with the first input, the second input of which is connected to the second output of the input block, and the output is connected. to the third input of the communication unit and format conversion.

The frame structure recovery unit contains a delay node, the output of which is connected to the single input of the first trigger, the zero inputs of which are connected respectively to the output of the decoder and the third input of the block. The single input of the second trigger is connected to the output of the first element I, the first input of which is co.din with the input of the delay node and the first input of the block. Second entrance

through the element is NOT connected to the output of the decoder. The zero input of the second trigger is connected to the output of the decoder, a single output connected to the first input of the second element And, the second input of which is connected to the output of the generator. The output of the second element I is connected to the first output of the block, the second output of which is connected to the output of the first trigger, the second input of the block through the counter is connected to the input of the decoder.

FIG. 1 shows a block diagram of the device; in fig. 2 is a functional block diagram of the restoration of the frame structure.

The device comprises a data input unit 1, a key 2, a communication unit and a format conversion 3, a frame structure recovery unit 4, buffer memory blocks 5 and 6, an interface block 7, an external memory block 8 and a control block 9.

The frame structure restoration block contains control inputs 10-12, output 13 on the key, output 14 on block 3 for issuing simulation sync pulses, delay node 15, trigger J6, HE element 17, AND 18 element, decoder 19, trigger 20, counter 21 , element And 22 and generator 23.

Let us consider three cases of device operation when preparing data having a frame structure: operation without failures, loss of one or several sync pulses within a frame, and the occurrence of one or several false sync pulses within a frame.

Before starting operation in all three cases, a control signal is output from the control unit 9 to the control input 10 of the frame structure recovery block 4, and the block 4 outputs the inhibitory potential to the control input 13 of key 2, after which the data input unit I is triggered. Sync pulses from block 1 are fed to the input of key 2 ,. frame end pulses - input 1 of the block 4 structure recovery block, and data bytes - on the information input of the communication block and format conversion 3. Data input from block 1 can start from an arbitrary channel in the frame. In order to provide input to the device from the first channel in the frame, the frame structure recovery unit 4 supports the inhibitory potential at input 13 of key 2 until the first end of frame pulse arrives. After that, the permitting potential is input to the input 13 of the key 2, and the sync pulses. The key 2 begins to enter the input of the communication unit and the format 3 conversion. On the first sync pulse, unit 3 writes the data bytes corresponding to this sync pulse to the first sector of the generated word, the second sync pulse is written the second byte of data in the second sector, etc., until the formation of the output word of the specified format is ensured. After that, the word is rewritten into one of the blocks of buffer memory 5, 6 ,. and a word ready signal is output to the input 12 of the frame structure recovery unit 4. The number of sectors in the output word is selected as a multiple of the channels in the frame, i.e. the frame contains an integer number of words. Similarly, the second word in the frame, the third and so on until the last word in the frame is formed, after which the frame structure restoration block 4 generates a inhibitory signal at input 13 of key 2. After 5 arrival of the end of frame pulse, permission is again given for input 13 of key 2, data byte of the next frame is packed into words and rewritten into a block of buffer memory (5, 6).

e So data is being prepared in the absence of failures.

The device works as follows.

If there are failures in the disappearance of one

or several clock pulses within

frame readiness words arrive at

5, input 12 of the frame structure recovery block 4, and the number of words issued in a given frame is counted. If the number of words output is less than the required number of channels in a frame and the number of sectors in a word at the end of the frame, then the frame structure recovery unit 4 simulates the output of sync pulses to the input 14 of the communication unit and the format 3 conversion until the number of words issued does not reach the required one, after which the imitation of the clock pulses stops. In sectors of words; generated by imitation sync pulses, zeros are written. that is, the physical values of the records are distorted (within one frame), but the structure of the records is preserved.

When one or more

false sync pulses within the frame. As in the first case, the frame structure recovery unit 4 counts the number of words issued within the frame of the frame after issuing the specified number of words gives the inhibitory potential to the input 13 of the key 2 and thus prohibits further passage of the sync pulses before the arrival of the end-of-frame pulse. After the arrival of the end-of-frame pulse, the frame structure recovery unit 4 removes the prohibition from the input 13 of the key 2, and the sync pulses belonging to the next frame are again fed to the communication unit and the format3 transformation.

The frame structure recovery unit 4 operates as follows. Before starting operation, the zero potential 10 of the trigger 16 is supplied to the control potential and the trigger 16 is set to the state “O”, and its inhibitory potential is formed at its single output 13, which prohibits the passage of sync pulses through the key 2 before the first pulse of the end of the frame (for so that data preparation can be started from the first channel in the frame).

The first pulse of the end of the frame through the delay block 15 sets the trigger 16 to the state I, the permit potential appears at its output 13, and the clock pulses begin to flow to the communication unit and format 3 conversions. The data bytes are packed into words and issued into the buffer memory block (5, 6). Readiness pulses

words arrive at input 12, are counted